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[PATCH][AArch64] Add constrain to address offset in storewb_pair/loadwb_pair insns
- From: Jiong Wang <jiong dot wang at arm dot com>
- To: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 29 Jul 2014 16:31:14 +0100
- Subject: [PATCH][AArch64] Add constrain to address offset in storewb_pair/loadwb_pair insns
- Authentication-results: sourceware.org; auth=none
Add a pridicate to check whether the const offset is valid.
For 32-bit variant: -256 <= offset <= 252
For 64-bit variant: -512 <= offset <= 504
no regression on aarch64-none-elf bare-metal.
2014-07-29 Renlin Li <renlin.li@arm.com>
2014-07-29 Jiong Wang <jiong.wang@arm.com>
gcc/
* config/aarch64/aarch64.c (offset_7bit_signed_scaled_p): Rename to
aarch64_offset_7bit_signed_scaled_p, remove static and use it .
* config/aarch64/aarch64-protos.h (aarch64_offset_7bit_signed_scaled_p): Declaration.
* config/aarch64/predicates.md (aarch64_mem_pair_offset): Define new predicate.
* config/aarch64/aarch64.md (loadwb_pair, storewb_pair): Use aarch64_mem_pair_offset.
ok to install ?
thanks.
From 26c1134bd0a1f20d9efacdae51acdd01f07f9eff Mon Sep 17 00:00:00 2001
From: Jiong Wang <jiong.wang@arm.com>
Date: Tue, 29 Jul 2014 15:06:04 +0100
Subject: [PATCH 2/2] [AArch64][2/2] Add predicate on load/store write back
pattern.
---
gcc/config/aarch64/aarch64-protos.h | 1 +
gcc/config/aarch64/aarch64.c | 12 ++++++------
gcc/config/aarch64/aarch64.md | 8 ++++----
gcc/config/aarch64/predicates.md | 4 ++++
4 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
index 53023ba..c8b832a 100644
--- a/gcc/config/aarch64/aarch64-protos.h
+++ b/gcc/config/aarch64/aarch64-protos.h
@@ -194,6 +194,7 @@ bool aarch64_modes_tieable_p (enum machine_mode mode1,
bool aarch64_move_imm (HOST_WIDE_INT, enum machine_mode);
bool aarch64_mov_operand_p (rtx, enum aarch64_symbol_context,
enum machine_mode);
+bool aarch64_offset_7bit_signed_scaled_p (enum machine_mode, HOST_WIDE_INT);
char *aarch64_output_scalar_simd_mov_immediate (rtx, enum machine_mode);
char *aarch64_output_simd_mov_immediate (rtx, enum machine_mode, unsigned);
bool aarch64_pad_arg_upward (enum machine_mode, const_tree);
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index ec0ac58..3ff0862 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3193,8 +3193,8 @@ aarch64_classify_index (struct aarch64_address_info *info, rtx x,
return false;
}
-static inline bool
-offset_7bit_signed_scaled_p (enum machine_mode mode, HOST_WIDE_INT offset)
+bool
+aarch64_offset_7bit_signed_scaled_p (enum machine_mode mode, HOST_WIDE_INT offset)
{
return (offset >= -64 * GET_MODE_SIZE (mode)
&& offset < 64 * GET_MODE_SIZE (mode)
@@ -3266,12 +3266,12 @@ aarch64_classify_address (struct aarch64_address_info *info,
We conservatively require an offset representable in either mode.
*/
if (mode == TImode || mode == TFmode)
- return (offset_7bit_signed_scaled_p (mode, offset)
+ return (aarch64_offset_7bit_signed_scaled_p (mode, offset)
&& offset_9bit_signed_unscaled_p (mode, offset));
if (outer_code == PARALLEL)
return ((GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
- && offset_7bit_signed_scaled_p (mode, offset));
+ && aarch64_offset_7bit_signed_scaled_p (mode, offset));
else
return (offset_9bit_signed_unscaled_p (mode, offset)
|| offset_12bit_unsigned_scaled_p (mode, offset));
@@ -3326,12 +3326,12 @@ aarch64_classify_address (struct aarch64_address_info *info,
We conservatively require an offset representable in either mode.
*/
if (mode == TImode || mode == TFmode)
- return (offset_7bit_signed_scaled_p (mode, offset)
+ return (aarch64_offset_7bit_signed_scaled_p (mode, offset)
&& offset_9bit_signed_unscaled_p (mode, offset));
if (outer_code == PARALLEL)
return ((GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)
- && offset_7bit_signed_scaled_p (mode, offset));
+ && aarch64_offset_7bit_signed_scaled_p (mode, offset));
else
return offset_9bit_signed_unscaled_p (mode, offset);
}
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 0728fb6..eac4664 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1022,7 +1022,7 @@
[(parallel
[(set (match_operand:P 0 "register_operand" "=k")
(plus:P (match_operand:P 1 "register_operand" "0")
- (match_operand:P 4 "const_int_operand" "n")))
+ (match_operand:P 4 "aarch64_mem_pair_offset" "n")))
(set (match_operand:GPI 2 "register_operand" "=r")
(mem:GPI (match_dup 1)))
(set (match_operand:GPI 3 "register_operand" "=r")
@@ -1037,7 +1037,7 @@
[(parallel
[(set (match_operand:P 0 "register_operand" "=k")
(plus:P (match_operand:P 1 "register_operand" "0")
- (match_operand:P 4 "const_int_operand" "n")))
+ (match_operand:P 4 "aarch64_mem_pair_offset" "n")))
(set (match_operand:GPF 2 "register_operand" "=w")
(mem:GPF (match_dup 1)))
(set (match_operand:GPF 3 "register_operand" "=w")
@@ -1054,7 +1054,7 @@
[(parallel
[(set (match_operand:P 0 "register_operand" "=&k")
(plus:P (match_operand:P 1 "register_operand" "0")
- (match_operand:P 4 "const_int_operand" "n")))
+ (match_operand:P 4 "aarch64_mem_pair_offset" "n")))
(set (mem:GPI (plus:P (match_dup 0)
(match_dup 4)))
(match_operand:GPI 2 "register_operand" "r"))
@@ -1070,7 +1070,7 @@
[(parallel
[(set (match_operand:P 0 "register_operand" "=&k")
(plus:P (match_operand:P 1 "register_operand" "0")
- (match_operand:P 4 "const_int_operand" "n")))
+ (match_operand:P 4 "aarch64_mem_pair_offset" "n")))
(set (mem:GPF (plus:P (match_dup 0)
(match_dup 4)))
(match_operand:GPF 2 "register_operand" "w"))
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 2702a3c..478de11 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -123,6 +123,10 @@
(match_test "INTVAL (op) != 0
&& (unsigned) exact_log2 (INTVAL (op)) < 64")))
+(define_predicate "aarch64_mem_pair_offset"
+ (and (match_code "const_int")
+ (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
+
(define_predicate "aarch64_mem_pair_operand"
(and (match_code "mem")
(match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), PARALLEL,
--
1.8.3