[PATCH][AArch64][2/2] Add CRC32 ACLE intrinsics testsuite

[Kyrill Tkachov <kyrylo dot tkachov at arm dot com>]

Hi all,

This is the testsuite for the CRC32 ACLE intrinsics. They are done in 
much the same way as the aarch32 tests in gcc.target/arm/acle/acle.exp 
except that these are modified to run at -O2 optimisation level.

These pass now on aarch64.

Ok for trunk after patch [1/2]?

Thanks,
Kyrill

2014-06-10  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    * gcc.target/aarch64/acle/acle.exp: New.
    * gcc.target/aarch64/acle/crc32b.c: New test.
    * gcc.target/aarch64/acle/crc32cb.c: Likewise.
    * gcc.target/aarch64/acle/crc32cd.c: Likewise.
    * gcc.target/aarch64/acle/crc32ch.c: Likewise.
    * gcc.target/aarch64/acle/crc32cw.c: Likewise.
    * gcc.target/aarch64/acle/crc32d.c: Likewise.
    * gcc.target/aarch64/acle/crc32h.c: Likewise.
    * gcc.target/aarch64/acle/crc32w.c: Likewise.

commit 02d00c53305ebd5c21ce48a427d3a1b97563b504
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Fri May 16 17:48:40 2014 +0100

    [AArch64] CRC32 ACLE intrinsics testsuite.

diff --git a/gcc/testsuite/gcc.target/aarch64/acle/acle.exp b/gcc/testsuite/gcc.target/aarch64/acle/acle.exp
new file mode 100644
index 0000000..e820f6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/acle.exp
@@ -0,0 +1,35 @@
+# Copyright (C) 2014 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't an AArch64 target.
+if ![istarget aarch64*-*-*] then {
+  return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
+	"" ""
+
+# All done.
+dg-finish
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32b.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32b.c
new file mode 100644
index 0000000..bf9a3d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32b.c
@@ -0,0 +1,15 @@
+/* Test the crc32b ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
+
+#include "arm_acle.h"
+
+uint32_t
+test_crc32b (uint32_t arg0, uint8_t arg1)
+{
+  return __crc32b (arg0, arg1);
+}
+
+/* { dg-final { scan-assembler "crc32b\tw..?, w..?, w..?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32cb.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32cb.c
new file mode 100644
index 0000000..a5a39b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32cb.c
@@ -0,0 +1,15 @@
+/* Test the crc32cb ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
+
+#include "arm_acle.h"
+
+uint32_t
+test_crc32cb (uint32_t arg0, uint8_t arg1)
+{
+  return __crc32cb (arg0, arg1);
+}
+
+/* { dg-final { scan-assembler "crc32cb\tw..?, w..?, w..?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32cd.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32cd.c
new file mode 100644
index 0000000..b50097a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32cd.c
@@ -0,0 +1,15 @@
+/* Test the crc32cd ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
+
+#include "arm_acle.h"
+
+uint32_t
+test_crc32cd (uint32_t arg0, uint64_t arg1)
+{
+  return __crc32cd (arg0, arg1);
+}
+
+/* { dg-final { scan-assembler "crc32cx\tw..?, w..?, x..?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32ch.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32ch.c
new file mode 100644
index 0000000..523faa2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32ch.c
@@ -0,0 +1,15 @@
+/* Test the crc32ch ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
+
+#include "arm_acle.h"
+
+uint32_t
+test_crc32ch (uint32_t arg0, uint16_t arg1)
+{
+  return __crc32ch (arg0, arg1);
+}
+
+/* { dg-final { scan-assembler "crc32ch\tw..?, w..?, w..?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32cw.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32cw.c
new file mode 100644
index 0000000..531e604
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32cw.c
@@ -0,0 +1,15 @@
+/* Test the crc32cw ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
+
+#include "arm_acle.h"
+
+uint32_t
+test_crc32cw (uint32_t arg0, uint32_t arg1)
+{
+  return __crc32cw (arg0, arg1);
+}
+
+/* { dg-final { scan-assembler "crc32cw\tw..?, w..?, w..?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32d.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32d.c
new file mode 100644
index 0000000..14fa627
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32d.c
@@ -0,0 +1,15 @@
+/* Test the crc32d ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
+
+#include "arm_acle.h"
+
+uint32_t
+test_crc32d (uint32_t arg0, uint64_t arg1)
+{
+  return __crc32d (arg0, arg1);
+}
+
+/* { dg-final { scan-assembler "crc32x\tw..?, w..?, x..?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32h.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32h.c
new file mode 100644
index 0000000..90819e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32h.c
@@ -0,0 +1,15 @@
+/* Test the crc32h ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
+
+#include "arm_acle.h"
+
+uint32_t
+test_crc32h (uint32_t arg0, uint16_t arg1)
+{
+  return __crc32h (arg0, arg1);
+}
+
+/* { dg-final { scan-assembler "crc32h\tw..?, w..?, w..?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/crc32w.c b/gcc/testsuite/gcc.target/aarch64/acle/crc32w.c
new file mode 100644
index 0000000..006f176
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/crc32w.c
@@ -0,0 +1,15 @@
+/* Test the crc32w ACLE intrinsic.  */
+
+/* { dg-do assemble } */
+/* { dg-options "-save-temps -O2 -march=armv8-a+crc" } */
+
+#include "arm_acle.h"
+
+uint32_t
+test_crc32w (uint32_t arg0, uint32_t arg1)
+{
+  return __crc32w (arg0, arg1);
+}
+
+/* { dg-final { scan-assembler "crc32w\tw..?, w..?, w..?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */