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Re: [patch i386]: Fix PR/46219 Generate indirect jump instruction
- From: Kai Tietz <ktietz70 at googlemail dot com>
- To: Richard Henderson <rth at redhat dot com>
- Cc: Kai Tietz <ktietz at redhat dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>, Jeff Law <law at redhat dot com>
- Date: Thu, 5 Jun 2014 18:47:49 +0200
- Subject: Re: [patch i386]: Fix PR/46219 Generate indirect jump instruction
- Authentication-results: sourceware.org; auth=none
- References: <1705189073 dot 20810228 dot 1401825417250 dot JavaMail dot zimbra at redhat dot com> <538E2ACC dot 5070403 at redhat dot com> <1140574607 dot 20834254 dot 1401826531982 dot JavaMail dot zimbra at redhat dot com> <538E31DB dot 6020904 at redhat dot com> <CAEwic4b5ihc7dPLWg8No++DwgNtLW1=Jfkk1Dvqnf4DyH==syA at mail dot gmail dot com> <538F7A9A dot 3090503 at redhat dot com>
Thanks for all your hints. Here is the updated patch
ChangeLog testsuite
2014-06-05 Kai Tietz <ktietz@redhat.com>
PR target/46219
* gcc.target/i386/sibcall-4.c: Remove xfail.
ChangeLog
2014-06-05 Kai Tietz <ktietz@redhat.com>
Richard Henderson <rth@redhat.com>
PR target/46219
* config/i386/predicates.md (memory_nox32_operand): Add memory_operand
checking for !TARGET_X32.
* config/i386/i386.md (UNSPEC_PEEPSIB): New unspec constant.
(sibcall_intern): New define_insn, plus required peepholes.
(sibcall_pop_intern): Likewise.
(sibcall_value_intern): Likewise.
(sibcall_value_pop_intern): Likewise.
Tested for i686-w64-mingw32, x86_64-unknown-linux-gnu. Ok for apply?
Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md (Revision 211255)
+++ config/i386/i386.md (Arbeitskopie)
@@ -111,6 +111,7 @@
UNSPEC_LEA_ADDR
UNSPEC_XBEGIN_ABORT
UNSPEC_STOS
+ UNSPEC_PEEPSIB
;; For SSE/MMX support:
UNSPEC_FIX_NOTRUNC
@@ -11382,6 +11383,53 @@
"* return ix86_output_call_insn (insn, operands[0]);"
[(set_attr "type" "call")])
+(define_insn "*sibcall_intern"
+ [(call (unspec [(mem:QI (match_operand:W 0 "memory_operand"))]
+ UNSPEC_PEEPSIB)
+ (match_operand 1))]
+ ""
+ "* return ix86_output_call_insn (insn, operands[0]);"
+ [(set_attr "type" "call")])
+
+(define_peephole2
+ [(set (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "memory_nox32_operand"))
+ (call (mem:QI (match_dup 0))
+ (match_operand 3))]
+ "TARGET_64BIT && SIBLING_CALL_P (peep2_next_insn (1))"
+ [(call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB)
+ (match_dup 3))])
+
+(define_peephole2
+ [(set (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "memory_nox32_operand"))
+ (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (call (mem:QI (match_dup 0))
+ (match_operand 3))]
+ "TARGET_64BIT && SIBLING_CALL_P (peep2_next_insn (2))"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB)
+ (match_dup 3))])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "memory_nox32_operand"))
+ (call (mem:QI (match_dup 0))
+ (match_operand 3))]
+ "!TARGET_64BIT && SIBLING_CALL_P (peep2_next_insn (1))"
+ [(call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB)
+ (match_dup 3))])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "memory_nox32_operand"))
+ (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (call (mem:QI (match_dup 0))
+ (match_operand 3))]
+ "!TARGET_64BIT && SIBLING_CALL_P (peep2_next_insn (2))"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB) (match_dup 3))])
+
(define_expand "call_pop"
[(parallel [(call (match_operand:QI 0)
(match_operand:SI 1))
@@ -11415,6 +11463,43 @@
"* return ix86_output_call_insn (insn, operands[0]);"
[(set_attr "type" "call")])
+(define_insn "*sibcall_pop_intern"
+ [(call (unspec [(mem:QI (match_operand:SI 0 "memory_operand"))]
+ UNSPEC_PEEPSIB)
+ (match_operand 1))
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 2 "immediate_operand" "i")))]
+ "!TARGET_64BIT"
+ "* return ix86_output_call_insn (insn, operands[0]);"
+ [(set_attr "type" "call")])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "memory_nox32_operand"))
+ (parallel [(call (mem:QI (match_dup 0))
+ (match_operand 3))
+ (set (reg:SI SP_REG)
+ (match_operand 4))])]
+ "!TARGET_64BIT && SIBLING_CALL_P (peep2_next_insn (1))"
+ [(parallel [(call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB)
+ (match_dup 3))
+ (set (reg:SI SP_REG) (match_dup 4))])])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "memory_nox32_operand"))
+ (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (parallel [(call (mem:QI (match_dup 0))
+ (match_operand 3))
+ (set (reg:SI SP_REG)
+ (match_operand 4))])]
+ "!TARGET_64BIT && SIBLING_CALL_P (peep2_next_insn (2))"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (parallel [(call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB)
+ (match_dup 3))
+ (set (reg:SI SP_REG) (match_dup 4))])])
+
;; Call subroutine, returning value in operand 0
(define_expand "call_value"
@@ -11457,6 +11542,63 @@
"* return ix86_output_call_insn (insn, operands[1]);"
[(set_attr "type" "callv")])
+(define_insn "*sibcall_value_intern"
+ [(set (match_operand 0)
+ (call (unspec [(mem:QI (match_operand:W 1 "memory_operand"))]
+ UNSPEC_PEEPSIB)
+ (match_operand 2)))]
+ ""
+ "* return ix86_output_call_insn (insn, operands[1]);"
+ [(set_attr "type" "callv")])
+
+(define_peephole2
+ [(set (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "memory_nox32_operand"))
+ (set (match_operand 2)
+ (call (mem:QI (match_dup 0))
+ (match_operand 3)))]
+ "TARGET_64BIT && SIBLING_CALL_P (peep2_next_insn (1))"
+ [(set (match_dup 2)
+ (call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB)
+ (match_dup 3)))])
+
+(define_peephole2
+ [(set (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "memory_nox32_operand"))
+ (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (set (match_operand 2)
+ (call (mem:QI (match_dup 0))
+ (match_operand 3)))]
+ "TARGET_64BIT && SIBLING_CALL_P (peep2_next_insn (2))"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (set (match_dup 2)
+ (call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB)
+ (match_dup 3)))])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "memory_nox32_operand"))
+ (set (match_operand 2)
+ (call (mem:QI (match_dup 0))
+ (match_operand 3)))]
+ "!TARGET_64BIT && SIBLING_CALL_P (peep2_next_insn (1))"
+ [(set (match_dup 2)
+ (call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB)
+ (match_dup 3)))])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "memory_nox32_operand"))
+ (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (set (match_operand 2)
+ (call (mem:QI (match_dup 0))
+ (match_operand 3)))]
+ "!TARGET_64BIT && SIBLING_CALL_P (peep2_next_insn (2))"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (set (match_dup 2)
+ (call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB)
+ (match_dup 3)))])
+
(define_insn "*call_value_rex64_ms_sysv"
[(match_parallel 3 "call_rex64_ms_sysv_operation"
[(set (match_operand 0)
@@ -11503,6 +11645,56 @@
"* return ix86_output_call_insn (insn, operands[1]);"
[(set_attr "type" "callv")])
+(define_insn "*sibcall_value_pop_intern"
+ [(set (match_operand 0)
+ (call (unspec [(mem:QI (match_operand:SI 1 "memory_operand"))]
+ UNSPEC_PEEPSIB)
+ (match_operand 2)))
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 3 "immediate_operand" "i")))]
+ "!TARGET_64BIT"
+ "* return ix86_output_call_insn (insn, operands[1]);"
+ [(set_attr "type" "callv")])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "memory_nox32_operand"))
+ (parallel [(set (match_operand 2)
+ (call (mem:QI (match_dup 0))
+ (match_operand 3)))
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 4 "immediate_operand")))]
+ )]
+ "!TARGET_64BIT && SIBLING_CALL_P (peep2_next_insn (1))"
+ [(parallel [(set (match_dup 2)
+ (call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB)
+ (match_dup 3)))
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (match_dup 4)))])])
+
+(define_peephole2
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "memory_nox32_operand"))
+ (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (parallel [(set (match_operand 2)
+ (call (mem:QI (match_dup 0))
+ (match_operand 3)))
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (match_operand:SI 4 "immediate_operand")))]
+ )]
+ "!TARGET_64BIT && SIBLING_CALL_P (peep2_next_insn (1))"
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
+ (parallel [(set (match_dup 2)
+ (call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB)
+ (match_dup 3)))
+ (set (reg:SI SP_REG)
+ (plus:SI (reg:SI SP_REG)
+ (match_dup 4)))])])
+
;; Call subroutine returning any type.
(define_expand "untyped_call"
Index: config/i386/predicates.md
===================================================================
--- config/i386/predicates.md (Revision 211255)
+++ config/i386/predicates.md (Arbeitskopie)
@@ -587,6 +587,11 @@
(ior (match_operand 0 "register_no_elim_operand")
(match_operand 0 "immediate_operand")))
+;; Test for a valid memory operand.
+(define_predicate "memory_nox32_operand"
+ (and (not (match_test "TARGET_X32"))
+ (match_operand 0 "memory_operand")))
+
;; Test for a valid operand for indirect branch.
(define_predicate "indirect_branch_operand"
(ior (match_operand 0 "register_operand")
Index: gcc.target/i386/sibcall-4.c
===================================================================
--- gcc.target/i386/sibcall-4.c (Revision 211255)
+++ gcc.target/i386/sibcall-4.c (Arbeitskopie)
@@ -11,4 +11,4 @@ void male_indirect_jump (long offset)
dispatch[offset](offset);
}
-/* { dg-final { scan-assembler-not "jmp\[ \t\]*.%eax" { xfail *-*-* } } } */
+/* { dg-final { scan-assembler-not "jmp\[ \t\]*.%eax" } } */