Re: [PATCH] Fix PR54733 Optimize endian independent load/store

[Richard Biener <richard dot guenther at gmail dot com>]

On Tue, May 20, 2014 at 4:46 AM, Thomas Preud'homme
<thomas.preudhomme@arm.com> wrote:
>> From: Richard Biener [mailto:richard.guenther@gmail.com]
>>
>> Agreed, but I am happy with doing that as a followup.  Btw,
>> a very simple one would be to reject unaligned
>> SLOW_UNALIGNED_ACCESS (TYPE_MODE (load_type), align).
>> [of course that may be true on MIPS even for the cases where
>> a "reasonable" fast unalgined variant exists - nearly no target
>> defines that macro in a too fancy way]
>
> Indeed, it's defined to 1 without consideration of the mode or alignment
> At least ARM, alpha, tilegx, tilepro and all target with STRICT_ALIGNMENT
> since that's the default value for SLOW_UNALIGNED_ACCESS macro. Thus
> mips should be in there too for instance.
>
> However, I fail to see how the code produced to do an unaligned load
> could be worse than the manual load done in the original bitwise
> expression. It might be worse for load + bswap though. Maybe I could
> skip the optimization based on this macro only for bswap?

It may do three aligned loads, char, short, char and combine them
while doing an unaligned int load may end up being slower.  Though
very probable the RTL expansion machinery for unaligned loads
is way more clever to emit an optimal sequence than a programmer is.

Anyway, as said before please consider addressing any cost issues
as followup - just make sure to properly emit unaligned loads via
a sequence I suggested.

Thanks,
Richard.

> Best regards,
>
> Thomas
>
>