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Re: Changing the MIPS ISA for the Loongson 3A from MIPS64 to MIPS64r2
- From: Richard Sandiford <rdsandiford at googlemail dot com>
- To: Andrew Bennett <Andrew dot Bennett at imgtec dot com>
- Cc: gcc-patches at gcc dot gnu dot org, Heiher <r at hev dot cc>
- Date: Tue, 04 Mar 2014 21:40:07 +0000
- Subject: Re: Changing the MIPS ISA for the Loongson 3A from MIPS64 to MIPS64r2
- Authentication-results: sourceware.org; auth=none
- References: <0DA23CC379F5F945ACB41CF394B98277531631 at LEMAIL01 dot le dot imgtec dot org> <87ha7j8b1v dot fsf at sandifor-thinkpad dot stglab dot manchester dot uk dot ibm dot com>
Richard Sandiford <rdsandiford@googlemail.com> writes:
> Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
>> Hi,
>>
>> I have noticed that a patch was placed in bugzilla to do this change, but it
>> does not appear to have been pushed. I was wondering if anyone could comment
>> why this is the case?
>>
>> The bugzilla URL is the following:
>>
>> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57754
>
> Looks OK if it passes testing. We'll need a name and email address for
> the commit though.
Following the discussion on binutils@ I committed the patch as follows.
I slightly tweaked it so that the MIPS64r2 processors stayed in
alphabetical order (which also means that mips-tables.opt doesn't
need to be regenerated).
Sorry again for the delay.
Thanks,
Richard
gcc/
2014-03-04 Heiher <r@hev.cc>
* config/mips/mips-cpus.def (loongson3a): Mark as a MIPS64r2 processor.
* config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Adjust accordingly.
Index: gcc/config/mips/mips-cpus.def
===================================================================
--- gcc/config/mips/mips-cpus.def 2014-01-02 22:16:09.524330756 +0000
+++ gcc/config/mips/mips-cpus.def 2014-03-04 21:22:32.970580383 +0000
@@ -145,9 +145,9 @@ MIPS_CPU ("sb1", PROCESSOR_SB1, 64, PTF_
MIPS_CPU ("sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY)
-MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY)
/* MIPS64 Release 2 processors. */
+MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 65, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)
MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY)
Index: gcc/config/mips/mips.h
===================================================================
--- gcc/config/mips/mips.h 2014-03-04 21:21:34.930071765 +0000
+++ gcc/config/mips/mips.h 2014-03-04 21:22:32.972580400 +0000
@@ -701,8 +701,8 @@ #define MIPS_ISA_LEVEL_SPEC \
%{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
|march=34k*|march=74k*|march=m14k*|march=1004k*: -mips32r2} \
%{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
- |march=xlr|march=loongson3a: -mips64} \
- %{march=mips64r2|march=octeon|march=xlp: -mips64r2} \
+ |march=xlr: -mips64} \
+ %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
%{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
/* A spec that infers a -mhard-float or -msoft-float setting from an