Re: [PATCH v4] PR middle-end/60281

[lin zuojian <manjian2006 at gmail dot com>]

Hi Jakub,
    Any comments on this patch?
--
Regards
lin zuojian

On Tue, Feb 25, 2014 at 03:28:14PM +0800, lin zuojian wrote:
> Sorry,I have forgot setting another shadow_mem's align.And many strbs
> bump up.
> Here 's patch v4.(last one contains html,damn thunderbird).
> 
> --
> Without aligning the asan stack base,this base will only 64-bit aligned
> in ARM machines.
> But asan require 256-bit aligned base because of this:
> 1.right shift take ASAN_SHADOW_SHIFT(which is 3) bits are zeros
> 2.store multiple/load multiple instructions require the other 2 bits are
> zeros
> 
> that add up lowest 5 bits should be zeros.That means 32 bytes or 256
> bits aligned.
> 
> * asan.c (asan_emit_stack_protection): Forcing the base to align to 256
> bits if STRICT_ALIGNMENT.
> And set shadow_mem align to 256 bits if STRICT_ALIGNMENT
> * cfgexpand.c (expand_stack_vars): set base_align appropriately when
> asan is on
> (expand_used_vars): Leaving a space in the stack frame for alignment if
> STRICT_ALIGNMENT
> ---
> gcc/asan.c | 14 ++++++++++++++
> gcc/cfgexpand.c | 13 ++++++++++++-
> 2 files changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/gcc/asan.c b/gcc/asan.c
> index 53992a8..64898cd 100644
> --- a/gcc/asan.c
> +++ b/gcc/asan.c
> @@ -1017,8 +1017,16 @@ asan_emit_stack_protection (rtx base, rtx pbase,
> unsigned int alignb,
> base_align_bias = ((asan_frame_size + alignb - 1)
> & ~(alignb - HOST_WIDE_INT_1)) - asan_frame_size;
> }
> + /* Align base if target is STRICT_ALIGNMENT. */
> + if (STRICT_ALIGNMENT)
> + base = expand_binop (Pmode, and_optab, base,
> + gen_int_mode (-((GET_MODE_ALIGNMENT (SImode) << ASAN_SHADOW_SHIFT) /
> BITS_PER_UNIT), Pmode),
> + NULL_RTX, 1, OPTAB_DIRECT);
> +
> if (use_after_return_class == -1 && pbase)
> emit_move_insn (pbase, base);
> +
> +
> base = expand_binop (Pmode, add_optab, base,
> gen_int_mode (base_offset - base_align_bias, Pmode),
> NULL_RTX, 1, OPTAB_DIRECT);
> @@ -1097,6 +1105,8 @@ asan_emit_stack_protection (rtx base, rtx pbase,
> unsigned int alignb,
> && (ASAN_RED_ZONE_SIZE >> ASAN_SHADOW_SHIFT) == 4);
> shadow_mem = gen_rtx_MEM (SImode, shadow_base);
> set_mem_alias_set (shadow_mem, asan_shadow_set);
> + if (STRICT_ALIGNMENT)
> + set_mem_align(shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
> prev_offset = base_offset;
> for (l = length; l; l -= 2)
> {
> @@ -1186,6 +1196,10 @@ asan_emit_stack_protection (rtx base, rtx pbase,
> unsigned int alignb,
> 
> shadow_mem = gen_rtx_MEM (BLKmode, shadow_base);
> set_mem_alias_set (shadow_mem, asan_shadow_set);
> +
> + if (STRICT_ALIGNMENT)
> + set_mem_align(shadow_mem, (GET_MODE_ALIGNMENT (SImode)));
> +
> prev_offset = base_offset;
> last_offset = base_offset;
> last_size = 0;
> diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
> index 06d494c..14fd1c2 100644
> --- a/gcc/cfgexpand.c
> +++ b/gcc/cfgexpand.c
> @@ -1013,10 +1013,18 @@ expand_stack_vars (bool (*pred) (size_t), struct
> stack_vars_data *data)
> if (data->asan_base == NULL)
> data->asan_base = gen_reg_rtx (Pmode);
> base = data->asan_base;
> +
> + if (!STRICT_ALIGNMENT)
> + base_align = crtl->max_used_stack_slot_alignment;
> + else
> + base_align = MAX(crtl->max_used_stack_slot_alignment,
> + (GET_MODE_ALIGNMENT (SImode) << ASAN_SHADOW_SHIFT));
> }
> else
> + {
> offset = alloc_stack_frame_space (stack_vars[i].size, alignb);
> - base_align = crtl->max_used_stack_slot_alignment;
> + base_align = crtl->max_used_stack_slot_alignment;
> + }
> }
> else
> {
> @@ -1843,6 +1851,9 @@ expand_used_vars (void)
> = alloc_stack_frame_space (redzonesz, ASAN_RED_ZONE_SIZE);
> data.asan_vec.safe_push (prev_offset);
> data.asan_vec.safe_push (offset);
> + /* Leave a space for alignment if STRICT_ALIGNMENT. */
> + if (STRICT_ALIGNMENT)
> + alloc_stack_frame_space ((GET_MODE_ALIGNMENT (SImode) <<
> ASAN_SHADOW_SHIFT) / BITS_PER_UNIT , 1);
> 
> var_end_seq
> = asan_emit_stack_protection (virtual_stack_vars_rtx,
> -- 
> 1.8.3.2
>