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Re: [Patch, i386] PR 59422 - Support more targets for function multi versioning
- From: Allan Sandfeld Jensen <carewolf at gmail dot com>
- To: "H.J. Lu" <hjl dot tools at gmail dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, "Gopalasubramanian, Ganesh" <Ganesh dot Gopalasubramanian at amd dot com>, Uros Bizjak <ubizjak at gmail dot com>
- Date: Mon, 23 Dec 2013 19:33:05 +0100
- Subject: Re: [Patch, i386] PR 59422 - Support more targets for function multi versioning
- Authentication-results: sourceware.org; auth=none
- References: <201312151954 dot 38590 dot linux at carewolf dot com> <201312231757 dot 57768 dot linux at carewolf dot com> <CAMe9rOr8iaSUyyvQgaKqJeXomB-xj07PiA_GrRpyjW+QKKK8Vw at mail dot gmail dot com>
On Monday 23 December 2013, H.J. Lu wrote:
> On Mon, Dec 23, 2013 at 8:57 AM, Allan Sandfeld Jensen
>
> <carewolf@gmail.com> wrote:
> > On Monday 23 December 2013, Allan Sandfeld Jensen wrote:
> >> On Monday 23 December 2013, H.J. Lu wrote:
> >> > On Thu, Dec 19, 2013 at 11:20:39AM +0100, Allan Sandfeld Jensen wrote:
> >> > > On Thursday 19 December 2013, Gopalasubramanian, Ganesh wrote:
> >> > > > > Sorry, I must have been looking at an older version, but as I
> >> > > > > said I already did enable it in the latest patch. (see
> >> > > > > http://gcc.gnu.org/ml/gcc-patches/2013-12/msg01577.html )
> >> > > >
> >> > > > Sorry for causing another revision but we would like to stick with
> >> > > > "btver1" and "btver2" rather than "BOBCAT" or "JAGUAR". Therefore
> >> > > > the changes would be like
> >> > >
> >> > > I will need to make an updated patch to move the new ISAs to the end
> >> > > of the list anyway. I will send it in a few days to give AMD or
> >> > > Intel developers time to comment on the current version.
> >> >
> >> > I renamed Intel processor names. Please update your patch. Here is my
> >> > patch to add more Intel processor support. You can add it to your
> >> > patch.
> >>
> >> Updated patch attached. Rebased, fixed coding style, moved new ISA enums
> >> to the end and applied H.J.Lu's patch.
> >
> > Fixed merging mistake that left haswell with SSE4_2 priority.
> >
> > `Allan
>
> + M_INTEL_COREI7_AVX,
> + M_INTEL_CORE_AVX2,
>
> Do we need them? M_INTEL_COREI7_AVX is the same
> M_INTEL_COREI7_SANDYBRIDGE and M_INTEL_CORE_AVX2
> is the same as M_INTEL_COREI7_HASWELL.
>
M_INTEL_COREI7_AVX is the common model for both sandybridge and ivybridge.
Matching PROCESSOR_SANDYBRIDGE, or march="corei7-avx". Similarly
M_INTEL_CORE_AVX2 is the common model for haswell and broadwell, matching
PROCESSOR_HASWELL or march="core-avx2".
> + M_INTEL_CORE_HASWELL
>
> Please change M_INTEL_CORE_HASWELL to M_INTEL_COREI7_HASWELL.
>
I used the name core_haswell to make its prefix match that of its model
core_avx2 (as opposed to corei7_avx for instance).
> + {"corei7-avx", M_INTEL_COREI7_AVX},
> + {"core-avx2", M_INTEL_CORE_AVX2},
>
> Why do we need them?
Without the existence of these entries, __attribute__((target("corei7-avx")))
or __attribute__((target("core-avx2")) failed to compile because of how
parameters to attributes were verified.
Regards
`Allan