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Re: [Patch, RTL] Eliminate redundant vec_select moves.


On 09 Dec 14:08, H.J. Lu wrote:
> 
> There are no regressions on Linux/x86-64 with -m32 and -m64.
> Can you check if it improves code quality on x886?

As second thought. If Tejas and Richard are right and it is simply incorrect
to check any offsets in this hook, may be we can end up with patch in the
bottom?

Test is passing (however I still don't know how to prohibit it for 32 bit x86),
bootstrap in progress.

Ideas?

This change belongs to rth.

--
Thanks, K

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 382f8fb..0d0bb67 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -35002,22 +35002,13 @@ ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
   if (MAYBE_FLOAT_CLASS_P (regclass))
     return true;
 
-  if (MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
-    {
-      /* Vector registers do not support QI or HImode loads.  If we don't
-	 disallow a change to these modes, reload will assume it's ok to
-	 drop the subreg from (subreg:SI (reg:HI 100) 0).  This affects
-	 the vec_dupv4hi pattern.  */
-      if (GET_MODE_SIZE (from) < 4)
-	return true;
-
-      /* Vector registers do not support subreg with nonzero offsets, which
-	 are otherwise valid for integer registers.  Since we can't see
-	 whether we have a nonzero offset from here, prohibit all
-         nonparadoxical subregs changing size.  */
-      if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from))
-	return true;
-    }
+  /* Vector registers do not support QI or HImode loads.  If we don't
+     disallow a change to these modes, reload will assume it's ok to
+     drop the subreg from (subreg:SI (reg:HI 100) 0).  This affects
+     the vec_dupv4hi pattern.  */
+  if ((MAYBE_SSE_CLASS_P (regclass) || MAYBE_MMX_CLASS_P (regclass))
+      && (GET_MODE_SIZE (from) < 4))
+    return true;
 
   return false;
 }
diff --git a/gcc/testsuite/gcc.dg/vect/vect-nop-move.c b/gcc/testsuite/gcc.dg/vect/vect-nop-move.c
index 1941933..e863c1b 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-nop-move.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-nop-move.c
@@ -1,4 +1,4 @@
-/* { dg-do run } */ 
+/* { dg-do run } */
 /* { dg-require-effective-target vect_float } */
 /* { dg-options "-O3 -fdump-rtl-combine-details" } */
 
@@ -16,9 +16,15 @@ foo32x4_be (float32x4_t x)
 }
 
 NOINLINE float
-foo32x4_le (float32x4_t x)
+bar_2 (float a, float b)
 {
-  return x[0];
+  return a;
+}
+
+NOINLINE float
+foo32x4_le (float32x4_t x, float32x4_t y)
+{
+  return bar_2 (x[0], y[0]);
 }
 
 NOINLINE float
@@ -30,12 +36,18 @@ bar (float a)
 NOINLINE float
 foo32x2_be (float32x2_t x)
 {
+#ifdef __i386__
+  __builtin_ia32_emms ();
+#endif
   return bar (x[1]);
 }
 
 NOINLINE float
 foo32x2_le (float32x2_t x)
 {
+#ifdef __i386__
+  __builtin_ia32_emms ();
+#endif
   return bar (x[0]);
 }
 
@@ -48,7 +60,7 @@ main()
   if (foo32x4_be (a) != 3.0f)
     abort ();
 
-  if (foo32x4_le (a) != 0.0f)
+  if (foo32x4_le (a, a) != 0.0f)
     abort ();
 
   if (foo32x2_be (b) != 1.0f)
@@ -60,5 +72,5 @@ main()
   return 0;
 }
 
-/* { dg-final { scan-rtl-dump "deleting noop move" "combine" { target aarch64*-*-* } } } */
+/* { dg-final { scan-rtl-dump "deleting noop move" "combine" { target { aarch64*-*-* || x86_64-*-* } } } } */
 /* { dg-final { cleanup-rtl-dump "combine" } } */


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