This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [PATCH, i386]: AMD bdver4 enablement
- From: Uros Bizjak <ubizjak at gmail dot com>
- To: "Gopalasubramanian, Ganesh" <Ganesh dot Gopalasubramanian at amd dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Wed, 13 Nov 2013 17:42:17 +0100
- Subject: Re: [PATCH, i386]: AMD bdver4 enablement
- Authentication-results: sourceware.org; auth=none
- References: <EB4625145972F94C9680D8CADD6516155C258171 at SATLEXDAG02 dot amd dot com>
On Tue, Nov 12, 2013 at 8:01 AM, Gopalasubramanian, Ganesh
<Ganesh.Gopalasubramanian@amd.com> wrote:
> The attached patch (bd4-enablement.patch) enables the next version of AMD's core.
> New addition to the ISA (AVX2 and BMI2) are enabled for the new core.
> Presently, the tuning is mostly copied from bdver3. This includes the pipeline modeling too.
> X86_TUNE_REASSOC_FP_TO_PARALLEL is not enabled (which might be a work in future).
>
> Bootstrapping passes. Is it OK for upstream?
>
> Regards
> Ganesh
>
> 2013-11-12 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
>
> * config.gcc (i[34567]86-*-linux* | ...): Add bdver4.
> (case ${target}): Add bdver4.
> * config/i386/bdver3.md: Add bdver4.
> * config/i386/driver-i386.c: (host_detect_local_cpu): Let
> -march=native recognize bdver4 processors.
> * config/i386/i386-c.c (ix86_target_macros_internal): Add
> bdver4 def_and_undef
> * config/i386/i386.c (struct processor_costs bdver4_cost): New.
> (m_BDVER4): New definition.
> (m_AMD_MULTIPLE): Includes m_BDVER4.
> (processor_target_table): Add bdver4 entry.
> (static const char *const cpu_names): Add bdver4 entry.
> (software_prefetching_beneficial_p): Add bdver3.
> (ix86_option_override_internal): Add bdver4 instruction sets.
> (ix86_issue_rate): Add bdver4.
> (ix86_adjust_cost): Add bdver4.
> (ia32_multipass_dfa_lookahead): Add bdver4.
> (enum processor_model): Add M_AMDFAM15H_BDVER4.
> (struct _arch_names_table): Add M_AMDFAM15H_BDVER4.
> (has_dispatch): Add bdver4.
> * config/i386/i386.h (TARGET_BDVER4): New definition.
> (enum target_cpu_default): Add TARGET_CPU_DEFAULT_bdver4.
> (enum processor_type): Add PROCESSOR_BDVER4.
> * config/i386/i386.md (define_attr "cpu"): Add bdver4.
> * config/i386/i386.opt (flag_dispatch_scheduler): Add bdver4.
> * gcc/doc/extend.texi: Add details about bdver4.
> * gcc/doc/invoke.texi: Add details about bdver4.
@@ -14526,6 +14526,11 @@ AMD Family 15h core based CPUs with x86-64
instruction set support. (This
supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE,
SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set
extensions.
+@item bdver4
+AMD Family 15h core based CPUs with x86-64 instruction set support. (This
+supersets BMI, BMI2, TBM, F16C, FMA, AVX, AVX2, XOP, LWP, AES, PCL_MUL, CX16,
+MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit
+instruction set extensions.
Please also mention FSGS and FMA4 (both are also missing for other
bdver targets).
OK with this change.
Uros.