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[PATCH][ARM] Create header file to put aarch32+aarch64 cores rtx cost tables in
- From: Kyrill Tkachov <kyrylo dot tkachov at arm dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Cc: Ramana Radhakrishnan <Ramana dot Radhakrishnan at arm dot com>, Richard Earnshaw <Richard dot Earnshaw at arm dot com>, Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>
- Date: Wed, 13 Nov 2013 09:06:20 +0000
- Subject: [PATCH][ARM] Create header file to put aarch32+aarch64 cores rtx cost tables in
- Authentication-results: sourceware.org; auth=none
Hi all,
Eventually we want to share rtx cost tables between arm and aarch64 (for
example, for ARMv8-A cores). This patch adds an aarch-cost-tables.h file where
we can put them.
We move the generic cost table in there as an example. The aarch64 backend will
have to modified in a separate patch to include this.
Tested arm-none-eabi on qemu.
Ok for trunk?
Thanks,
Kyrill
2013-11-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c: Include aarch-cost-tables.h.
(generic_extra_costs): Move from here...
* config/arm/aarch-cost-tables.h: ... To here. New file.diff --git a/gcc/config/arm/aarch-cost-tables.h b/gcc/config/arm/aarch-cost-tables.h
new file mode 100644
index 0000000..a15de78
--- /dev/null
+++ b/gcc/config/arm/aarch-cost-tables.h
@@ -0,0 +1,125 @@
+/* RTX cost tables shared between arm and aarch64.
+
+ Copyright (C) 2013 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef GCC_AARCH_COST_TABLES_H
+#define GCC_AARCH_COST_TABLES_H
+
+const struct cpu_cost_table generic_extra_costs =
+{
+ /* ALU */
+ {
+ 0, /* Arith. */
+ 0, /* Logical. */
+ 0, /* Shift. */
+ COSTS_N_INSNS (1), /* Shift_reg. */
+ 0, /* Arith_shift. */
+ COSTS_N_INSNS (1), /* Arith_shift_reg. */
+ 0, /* Log_shift. */
+ COSTS_N_INSNS (1), /* Log_shift_reg. */
+ 0, /* Extend. */
+ COSTS_N_INSNS (1), /* Extend_arith. */
+ 0, /* Bfi. */
+ 0, /* Bfx. */
+ 0, /* Clz. */
+ COSTS_N_INSNS (1), /* non_exec. */
+ false /* non_exec_costs_exec. */
+ },
+ {
+ /* MULT SImode */
+ {
+ COSTS_N_INSNS (2), /* Simple. */
+ COSTS_N_INSNS (1), /* Flag_setting. */
+ COSTS_N_INSNS (2), /* Extend. */
+ COSTS_N_INSNS (3), /* Add. */
+ COSTS_N_INSNS (3), /* Extend_add. */
+ COSTS_N_INSNS (8) /* Idiv. */
+ },
+ /* MULT DImode */
+ {
+ 0, /* Simple (N/A). */
+ 0, /* Flag_setting (N/A). */
+ COSTS_N_INSNS (2), /* Extend. */
+ 0, /* Add (N/A). */
+ COSTS_N_INSNS (3), /* Extend_add. */
+ 0 /* Idiv (N/A). */
+ }
+ },
+ /* LD/ST */
+ {
+ COSTS_N_INSNS (2), /* Load. */
+ COSTS_N_INSNS (2), /* Load_sign_extend. */
+ COSTS_N_INSNS (3), /* Ldrd. */
+ COSTS_N_INSNS (2), /* Ldm_1st. */
+ 1, /* Ldm_regs_per_insn_1st. */
+ 1, /* Ldm_regs_per_insn_subsequent. */
+ COSTS_N_INSNS (2), /* Loadf. */
+ COSTS_N_INSNS (3), /* Loadd. */
+ COSTS_N_INSNS (1), /* Load_unaligned. */
+ COSTS_N_INSNS (2), /* Store. */
+ COSTS_N_INSNS (3), /* Strd. */
+ COSTS_N_INSNS (2), /* Stm_1st. */
+ 1, /* Stm_regs_per_insn_1st. */
+ 1, /* Stm_regs_per_insn_subsequent. */
+ COSTS_N_INSNS (2), /* Storef. */
+ COSTS_N_INSNS (3), /* Stored. */
+ COSTS_N_INSNS (1) /* Store_unaligned. */
+ },
+ {
+ /* FP SFmode */
+ {
+ COSTS_N_INSNS (7), /* Div. */
+ COSTS_N_INSNS (2), /* Mult. */
+ COSTS_N_INSNS (3), /* Mult_addsub. */
+ COSTS_N_INSNS (3), /* Fma. */
+ COSTS_N_INSNS (1), /* Addsub. */
+ 0, /* Fpconst. */
+ 0, /* Neg. */
+ 0, /* Compare. */
+ 0, /* Widen. */
+ 0, /* Narrow. */
+ 0, /* Toint. */
+ 0, /* Fromint. */
+ 0 /* Roundint. */
+ },
+ /* FP DFmode */
+ {
+ COSTS_N_INSNS (15), /* Div. */
+ COSTS_N_INSNS (5), /* Mult. */
+ COSTS_N_INSNS (7), /* Mult_addsub. */
+ COSTS_N_INSNS (7), /* Fma. */
+ COSTS_N_INSNS (3), /* Addsub. */
+ 0, /* Fpconst. */
+ 0, /* Neg. */
+ 0, /* Compare. */
+ 0, /* Widen. */
+ 0, /* Narrow. */
+ 0, /* Toint. */
+ 0, /* Fromint. */
+ 0 /* Roundint. */
+ }
+ },
+ /* Vector */
+ {
+ COSTS_N_INSNS (1) /* Alu. */
+ }
+};
+
+#endif /* GCC_AARCH_COST_TABLES_H */
\ No newline at end of file
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index bd2fda6..21ece91 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -949,106 +949,9 @@ struct cpu_vec_costs arm_default_vec_cost = {
1, /* cond_not_taken_branch_cost. */
};
+/* Cost tables for AArch32 + AArch64 cores should go in aarch-cost-tables.h */
+#include "aarch-cost-tables.h"
-const struct cpu_cost_table generic_extra_costs =
-{
- /* ALU */
- {
- 0, /* Arith. */
- 0, /* Logical. */
- 0, /* Shift. */
- COSTS_N_INSNS (1), /* Shift_reg. */
- 0, /* Arith_shift. */
- COSTS_N_INSNS (1), /* Arith_shift_reg. */
- 0, /* Log_shift. */
- COSTS_N_INSNS (1), /* Log_shift_reg. */
- 0, /* Extend. */
- COSTS_N_INSNS (1), /* Extend_arith. */
- 0, /* Bfi. */
- 0, /* Bfx. */
- 0, /* Clz. */
- COSTS_N_INSNS (1), /* non_exec. */
- false /* non_exec_costs_exec. */
- },
- /* MULT SImode */
- {
- {
- COSTS_N_INSNS (2), /* Simple. */
- COSTS_N_INSNS (1), /* Flag_setting. */
- COSTS_N_INSNS (2), /* Extend. */
- COSTS_N_INSNS (3), /* Add. */
- COSTS_N_INSNS (3), /* Extend_add. */
- COSTS_N_INSNS (8) /* Idiv. */
- },
- /* MULT DImode */
- {
- 0, /* Simple (N/A). */
- 0, /* Flag_setting (N/A). */
- COSTS_N_INSNS (2), /* Extend. */
- 0, /* Add (N/A). */
- COSTS_N_INSNS (3), /* Extend_add. */
- 0 /* Idiv (N/A). */
- }
- },
- /* LD/ST */
- {
- COSTS_N_INSNS (2), /* Load. */
- COSTS_N_INSNS (2), /* Load_sign_extend. */
- COSTS_N_INSNS (3), /* Ldrd. */
- COSTS_N_INSNS (2), /* Ldm_1st. */
- 1, /* Ldm_regs_per_insn_1st. */
- 1, /* Ldm_regs_per_insn_subsequent. */
- COSTS_N_INSNS (2), /* Loadf. */
- COSTS_N_INSNS (3), /* Loadd. */
- COSTS_N_INSNS (1), /* Load_unaligned. */
- COSTS_N_INSNS (2), /* Store. */
- COSTS_N_INSNS (3), /* Strd. */
- COSTS_N_INSNS (2), /* Stm_1st. */
- 1, /* Stm_regs_per_insn_1st. */
- 1, /* Stm_regs_per_insn_subsequent. */
- COSTS_N_INSNS (2), /* Storef. */
- COSTS_N_INSNS (3), /* Stored. */
- COSTS_N_INSNS (1) /* Store_unaligned. */
- },
- {
- /* FP SFmode */
- {
- COSTS_N_INSNS (7), /* Div. */
- COSTS_N_INSNS (2), /* Mult. */
- COSTS_N_INSNS (3), /* Mult_addsub. */
- COSTS_N_INSNS (3), /* Fma. */
- COSTS_N_INSNS (1), /* Addsub. */
- 0, /* Fpconst. */
- 0, /* Neg. */
- 0, /* Compare. */
- 0, /* Widen. */
- 0, /* Narrow. */
- 0, /* Toint. */
- 0, /* Fromint. */
- 0 /* Roundint. */
- },
- /* FP DFmode */
- {
- COSTS_N_INSNS (15), /* Div. */
- COSTS_N_INSNS (5), /* Mult. */
- COSTS_N_INSNS (7), /* Mult_addsub. */
- COSTS_N_INSNS (7), /* Fma. */
- COSTS_N_INSNS (3), /* Addsub. */
- 0, /* Fpconst. */
- 0, /* Neg. */
- 0, /* Compare. */
- 0, /* Widen. */
- 0, /* Narrow. */
- 0, /* Toint. */
- 0, /* Fromint. */
- 0 /* Roundint. */
- }
- },
- /* Vector */
- {
- COSTS_N_INSNS (1) /* Alu. */
- }
-};
const struct cpu_cost_table cortexa7_extra_costs =
{