This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [ARM][PATCH] Fix testsuite testcase neon-vcond-[ltgt,unordered].c


On 10/24/13 00:04, Kugan wrote:
Hi,

arm testcases neon-vcond-ltgt.c and neon-vcond-unordered.c fails in
Linaro 4.8 branch. It is not reproducable with trunk but it can happen.
Both neon-vcond-ltgt.c and neon-vcond-unordered.c scans for vbsl
instruction, with other vector instructions. However, as per the comment
  for "neon_vbsl<mode>_internal" md pattern defined in neon.md, gcc can
generate vbsl or vbit or vbif depending on the register allocation.
Therfore, these testcases should scan for one of these three
instructions instead of just vbsl. I have updated the testcases to scan
vbsl or vbit or vbif now.

Is this OK?

Thanks,
Kugan


Hit send too soon on my earlier email. Minor nit in the Changelog as below. Need a newline between the DATE line and the file names .


2013-10-23  Kugan Vivekanandarajah  <kuganv@linaro.org>

	* gcc.target/arm/neon-vcond-ltgt.c: Scan for vbsl or vbit or vbif.
	* gcc.target/arm/neon-vcond-unordered.c: Scan for vbsl or vbit or vbif.




Ramana



Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]