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[SPARC] Add peephole for memory barriers
- From: Eric Botcazou <ebotcazou at adacore dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sun, 29 Sep 2013 19:53:04 +0200
- Subject: [SPARC] Add peephole for memory barriers
- Authentication-results: sourceware.org; auth=none
This is a bit gross, but this prevents consecutive memory barriers from being
generated, for example on accesses to atomic objects in Ada.
Tested on SPARC/Solaris, applied on the mainline.
2013-09-29 Eric Botcazou <ebotcazou@adacore.com>
* config/sparc/sync.md: Add peephole for consecutive memory barriers.
--
Eric Botcazou
Index: config/sparc/sync.md
===================================================================
--- config/sparc/sync.md (revision 202912)
+++ config/sparc/sync.md (working copy)
@@ -93,6 +93,18 @@ (define_insn "*membar"
"membar\t%1"
[(set_attr "type" "multi")])
+(define_peephole2
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
+ UNSPEC_MEMBAR))
+ (set (match_operand:BLK 2 "" "")
+ (unspec:BLK [(match_dup 2) (match_operand:SI 3 "const_int_operand")]
+ UNSPEC_MEMBAR))]
+ ""
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_dup 0) (match_dup 1)] UNSPEC_MEMBAR))]
+{ operands[1] = GEN_INT (UINTVAL (operands[1]) | UINTVAL (operands[3])); })
+
(define_expand "atomic_load<mode>"
[(match_operand:I 0 "register_operand" "")
(match_operand:I 1 "memory_operand" "")