[rl78] Add -mallregs

[DJ Delorie <dj at redhat dot com>]

GCC typically avoids using virtual registers $r24 through $r31, as
this register bank (bank 3) is reserved for hand-written assembly
interrupt handlers.  If unneeded for that, this new option lets gcc
use those registers also.  Committed.

	* config/rl78/constraints.md (Wcv): Allow up to $r31.
	* config/rl78/rl78.c (rl78_asm_file_start: Likewise.
	(rl78_option_override): Likewise, if -mallregs.
	(is_virtual_register): Likewise.
	* config/rl78/rl78.h (reg_class): Extend VREGS to $r31.
	(REGNO_OK_FOR_BASE_P): Likewise.
	* config/rl78/rl78.opt (-mallregs): New.

Index: config/rl78/rl78.h
===================================================================
--- config/rl78/rl78.h	(revision 202668)
+++ config/rl78/rl78.h	(working copy)
@@ -262,13 +262,13 @@ enum reg_class
   { 0x0000000c, 0x00000000 },	/* B and C - index regs.  */	\
   { 0x000000ff, 0x00000000 },	/* all real registers.  */	\
   { 0x00000000, 0x00000001 }, 	/* SP */			\
   { 0x00000300, 0x00000000 }, 	/* R8 - HImode */		\
   { 0x00000c00, 0x00000000 }, 	/* R10 - HImode */		\
   { 0xff000000, 0x00000000 }, 	/* INT - HImode */		\
-  { 0x007fff00, 0x00000000 },	/* Virtual registers.  */	\
+  { 0xff7fff00, 0x00000000 },	/* Virtual registers.  */	\
   { 0xff7fffff, 0x00000002 },	/* General registers.  */	\
   { 0x04000000, 0x00000004 },	/* PSW.  */	\
   { 0xff7fffff, 0x0000001f }	/* All registers.  */		\
 }
 
 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
@@ -349,13 +349,13 @@ enum reg_class
   (IN_RANGE ((REGNO), (MIN), (MAX)) 			\
    || (reg_renumber != NULL				\
        && reg_renumber[(REGNO)] >= (MIN)		\
        && reg_renumber[(REGNO)] <= (MAX)))
 
 #ifdef REG_OK_STRICT
-#define REGNO_OK_FOR_BASE_P(regno)      REGNO_IN_RANGE (regno, 16, 23)
+#define REGNO_OK_FOR_BASE_P(regno)      REGNO_IN_RANGE (regno, 16, 31)
 #else
 #define REGNO_OK_FOR_BASE_P(regno)	1
 #endif
 
 #define REGNO_OK_FOR_INDEX_P(regno)	REGNO_OK_FOR_BASE_P (regno)
 
Index: config/rl78/constraints.md
===================================================================
--- config/rl78/constraints.md	(revision 202668)
+++ config/rl78/constraints.md	(working copy)
@@ -260,16 +260,16 @@
   "es:[AX..HL] for calls"
   (match_test "rl78_es_addr (op) && satisfies_constraint_Cca (rl78_es_base (op))
                || satisfies_constraint_Cca (op)")
   )
 
 (define_memory_constraint "Ccv"
-  "[AX..HL,r8-r23] for calls"
+  "[AX..HL,r8-r31] for calls"
   (and (match_code "mem")
        (and (match_code "reg" "0")
-	    (match_test "REGNO (XEXP (op, 0)) < 24")))
+	    (match_test "REGNO (XEXP (op, 0)) < 31")))
   )
 (define_memory_constraint "Wcv"
   "es:[AX..HL,r8-r23] for calls"
   (match_test "rl78_es_addr (op) && satisfies_constraint_Ccv (rl78_es_base (op))
                || satisfies_constraint_Ccv (op)")
   )
Index: config/rl78/rl78.c
===================================================================
--- config/rl78/rl78.c	(revision 202668)
+++ config/rl78/rl78.c	(working copy)
@@ -269,12 +269,13 @@ rl78_asm_file_start (void)
   else
     {
       for (i = 0; i < 8; i++)
 	{
 	  fprintf (asm_out_file, "r%d\t=\t0x%x\n", 8 + i, 0xffef0 + i);
 	  fprintf (asm_out_file, "r%d\t=\t0x%x\n", 16 + i, 0xffee8 + i);
+	  fprintf (asm_out_file, "r%d\t=\t0x%x\n", 24 + i, 0xffee0 + i);
 	}
     }
 
   opt_pass *rl78_devirt_pass = make_pass_rl78_devirt (g);
   static struct register_pass_info rl78_devirt_info =
     {
@@ -306,12 +307,19 @@ rl78_option_override (void)
 {
   flag_omit_frame_pointer = 1;
   flag_no_function_cse = 1;
   flag_split_wide_types = 0;
 
   init_machine_status = rl78_init_machine_status;
+
+  if (TARGET_ALLREGS)
+    {
+      int i;
+      for (i=24; i<32; i++)
+	fixed_regs[i] = 0;
+    }
 }
 
 /* Most registers are 8 bits.  Some are 16 bits because, for example,
    gcc doesn't like dealing with $FP as a register pair.  This table
    maps register numbers to size in bytes.  */
 static const int register_sizes[] =
@@ -2212,13 +2220,13 @@ insn_ok_now (rtx insn)
 /* Returns TRUE if R is a virtual register.  */
 static bool
 is_virtual_register (rtx r)
 {
   return (GET_CODE (r) == REG
 	  && REGNO (r) >= 8
-	  && REGNO (r) < 24);
+	  && REGNO (r) < 32);
 }
 
 /* In all these alloc routines, we expect the following: the insn
    pattern is unshared, the insn was previously recognized and failed
    due to predicates or constraints, and the operand data is in
    recog_data.  */
Index: config/rl78/rl78.opt
===================================================================
--- config/rl78/rl78.opt	(revision 202668)
+++ config/rl78/rl78.opt	(working copy)
@@ -39,12 +39,16 @@ Enum(rl78_mul_types) String(none) Value(
 EnumValue
 Enum(rl78_mul_types) String(rl78) Value(MUL_RL78)
 
 EnumValue
 Enum(rl78_mul_types) String(g13) Value(MUL_G13)
 
+mallregs
+Target Mask(ALLREGS)
+Use all registers, reserving none for interrupt handlers.
+
 mrelax
 Target
 Enable assembler and linker relaxation.
 
 mg10
 Target Mask(G10)