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RE: [AARCH64][Insn classification unification 3/N] ALU/shift types
- From: James Greenhalgh <james dot greenhalgh at arm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: marcus dot shawcroft at arm dot com, ramana dot radhakrishnan at arm dot com, richard dot earnshaw at arm dot com
- Date: Mon, 19 Aug 2013 14:14:25 +0100
- Subject: RE: [AARCH64][Insn classification unification 3/N] ALU/shift types
- References: <5200BDFE dot 4070806 at arm dot com>
Hi Richard,
Thanks for looking at this patch.
> Why arlo_reg into just adc & adcs? Why not adc_reg and adcs_reg (with
> equivalent changes for arlo_imm?
Fixed.
> Why is adr factored out of arlo_reg rather than arlo_imm? adr is an
> add
> immediate using the PC register as a base.
Fixed.
>
> Finally, please, please, please(!) generate your .md file diffs with
> gnu
> diff's '-F ^(define' option. This makes it *much* easier to identify
> which pattern is being modified.
Hopefully, Fixed.
> And another point. Operations such as alu_ext and csel are
> architecturally impossible on pre-v8 cores, so there's no need to
> consider them in pre-armv8 pipeline descriptions.
Good catch, I've removed these hunks.
I've regression tested this spin of the patch on arm-none-eabi and
aarch64-none-elf and I've bootstrapped the compiler on a chromebook.
Also, I've run some sanity checking scripts to ensure that no
negative changes in scheduling occurred.
Is this OK for trunk?
Thanks
James
-----
2013-08-19 James Greenhalgh <james.greenhalgh@arm.com>
Sofiane Naci <sofiane.naci@arm.com>
* config/arm/types.md (define_attr "type"):
Expand "arlo_imm"
into "adr", "alu_imm", "alus_imm", "logic_imm", "logics_imm".
Expand "arlo_reg"
into "adc", "adcs", "alu_ext", "alu_reg", "alus_ext",
"alus_reg", "bfm", "csel", "logic_reg", "logics_reg", "rev".
Expand "arlo_shift"
into "alu_shift_imm", "alus_shift_imm", "logic_shift_imm",
"logics_shift_imm".
Expand "arlo_shift_reg"
into "alu_shift_reg", "alus_shift_reg", "logic_shift_reg",
"logics_shift_reg".
Expand "clz" into "clz, "rbit".
Rename "shift" to "shift_imm".
* config/arm/arm.md (define_attr "core_cycles"): Update for attribute
changes.
Update for attribute changes all occurrences of arlo_* and
shift* types.
* config/arm/arm-fixed.md: Update for attribute changes
all occurrences of arlo_* types.
* config/arm/thumb2.md: Update for attribute changes all occurrences
of arlo_* types.
* config/arm/arm.c (xscale_sched_adjust_cost): (rtx insn, rtx
(cortexa7_older_only): Likewise.
(cortexa7_younger): Likewise.
* config/arm/arm1020e.md (1020alu_op): Update for attribute changes.
(1020alu_shift_op): Likewise.
(1020alu_shift_reg_op): Likewise.
* config/arm/arm1026ejs.md (alu_op): Update for attribute changes.
(alu_shift_op): Likewise.
(alu_shift_reg_op): Likewise.
* config/arm/arm1136jfs.md (11_alu_op): Update for
attribute changes.
(11_alu_shift_op): Likewise.
(11_alu_shift_reg_op): Likewise.
* config/arm/arm926ejs.md (9_alu_op): Update for attribute changes.
(9_alu_shift_reg_op): Likewise.
* config/arm/cortex-a15.md (cortex_a15_alu): Update for
attribute changes.
(cortex_a15_alu_shift): Likewise.
(cortex_a15_alu_shift_reg): Likewise.
* config/arm/cortex-a5.md (cortex_a5_alu): Update for
attribute changes.
(cortex_a5_alu_shift): Likewise.
* config/arm/cortex-a53.md
(cortex_a53_alu): Update for attribute changes.
(cortex_a53_alu_shift): Likewise.
* config/arm/cortex-a7.md
(cortex_a7_alu_imm): Update for attribute changes.
(cortex_a7_alu_reg): Likewise.
(cortex_a7_alu_shift): Likewise.
* config/arm/cortex-a8.md
(cortex_a8_alu): Update for attribute changes.
(cortex_a8_alu_shift): Likewise.
(cortex_a8_alu_shift_reg): Likewise.
* config/arm/cortex-a9.md
(cortex_a9_dp): Update for attribute changes.
(cortex_a9_dp_shift): Likewise.
* config/arm/cortex-m4.md
(cortex_m4_alu): Update for attribute changes.
* config/arm/cortex-r4.md
(cortex_r4_alu): Update for attribute changes.
(cortex_r4_mov): Likewise.
(cortex_r4_alu_shift_reg): Likewise.
* config/arm/fa526.md
(526_alu_op): Update for attribute changes.
(526_alu_shift_op): Likewise.
* config/arm/fa606te.md
(606te_alu_op): Update for attribute changes.
* config/arm/fa626te.md
(626te_alu_op): Update for attribute changes.
(626te_alu_shift_op): Likewise.
* config/arm/fa726te.md
(726te_alu_op): Update for attribute changes.
(726te_alu_shift_op): Likewise.
(726te_alu_shift_reg_op): Likewise.
* config/arm/fmp626.md (mp626_alu_op): Update for attribute changes.
(mp626_alu_shift_op): Likewise.
* config/arm/marvell-pj4.md (pj4_alu): Update for attribute changes.
(pj4_alu_conds): Likewise.
(pj4_shift): Likewise.
(pj4_shift_conds): Likewise.
(pj4_alu_shift): Likewise.
(pj4_alu_shift_conds): Likewise.
* config/aarch64/aarch64.md: Update for attribute change
all occurrences of arlo_* and shift* types.
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 70603093287bc2c7b1bdcc21bfc8441f0e9681ee..b8cd9fae2756c9df067abd895686b7fac603dad3 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -828,8 +828,8 @@ (define_insn "*movsi_aarch64"
fmov\\t%w0, %s1
fmov\\t%s0, %s1"
[(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov")
- (set_attr "type" "mov_reg,mov_reg,mov_reg,arlo_reg,load1,load1,store1,store1,\
- mov_reg,mov_reg,mov_reg,mov_reg,mov_reg")
+ (set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
+ adr,adr,mov_reg,mov_reg,mov_reg")
(set_attr "mode" "SI")
(set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")]
)
@@ -856,7 +856,7 @@ (define_insn "*movdi_aarch64"
movi\\t%d0, %1"
[(set_attr "v8type" "move,move,move,alu,load1,load1,store1,store1,adr,adr,fmov,fmov,fmov,fmov")
(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,load1,load1,store1,store1,\
- mov_reg,mov_reg,mov_reg,mov_reg,mov_reg,mov_reg")
+ adr,adr,mov_reg,mov_reg,mov_reg,mov_reg")
(set_attr "mode" "DI")
(set_attr "fp" "*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*")
(set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,yes")]
@@ -1022,7 +1022,7 @@ (define_insn "*movtf_aarch64"
ldp\\t%0, %H0, %1
stp\\t%1, %H1, %0"
[(set_attr "v8type" "logic,move2,fmovi2f,fmovf2i,fconst,fconst,fpsimd_load,fpsimd_store,fpsimd_load2,fpsimd_store2")
- (set_attr "type" "arlo_reg,mov_reg,f_mcr,f_mrc,fconstd,fconstd,\
+ (set_attr "type" "logic_reg,mov_reg,f_mcr,f_mrc,fconstd,fconstd,\
f_loadd,f_stored,f_loadd,f_stored")
(set_attr "mode" "DF,DF,DF,DF,DF,DF,TF,TF,DF,DF")
(set_attr "length" "4,8,8,8,4,4,4,4,4,4")
@@ -1273,7 +1273,7 @@ (define_insn "*addsi3_aarch64"
add\\t%w0, %w1, %w2
sub\\t%w0, %w1, #%n2"
[(set_attr "v8type" "alu")
- (set_attr "type" "arlo_imm,arlo_reg,arlo_imm")
+ (set_attr "type" "alu_imm,alu_reg,alu_imm")
(set_attr "mode" "SI")]
)
@@ -1290,7 +1290,7 @@ (define_insn "*addsi3_aarch64_uxtw"
add\\t%w0, %w1, %w2
sub\\t%w0, %w1, #%n2"
[(set_attr "v8type" "alu")
- (set_attr "type" "arlo_imm,arlo_reg,arlo_imm")
+ (set_attr "type" "alu_imm,alu_reg,alu_imm")
(set_attr "mode" "SI")]
)
@@ -1307,7 +1307,7 @@ (define_insn "*adddi3_aarch64"
sub\\t%x0, %x1, #%n2
add\\t%d0, %d1, %d2"
[(set_attr "v8type" "alu")
- (set_attr "type" "arlo_imm,arlo_reg,arlo_imm,arlo_reg")
+ (set_attr "type" "alu_imm,alu_reg,alu_imm,alu_reg")
(set_attr "mode" "DI")
(set_attr "simd" "*,*,*,yes")]
)
@@ -1326,7 +1326,7 @@ (define_insn "*add<mode>3_compare0"
adds\\t%<w>0, %<w>1, %<w>2
subs\\t%<w>0, %<w>1, #%n2"
[(set_attr "v8type" "alus")
- (set_attr "type" "arlo_reg,arlo_imm,arlo_imm")
+ (set_attr "type" "alus_reg,alus_imm,alus_imm")
(set_attr "mode" "<MODE>")]
)
@@ -1345,7 +1345,7 @@ (define_insn "*addsi3_compare0_uxtw"
adds\\t%w0, %w1, %w2
subs\\t%w0, %w1, #%n2"
[(set_attr "v8type" "alus")
- (set_attr "type" "arlo_reg,arlo_imm,arlo_imm")
+ (set_attr "type" "alus_reg,alus_imm,alus_imm")
(set_attr "mode" "SI")]
)
@@ -1363,7 +1363,7 @@ (define_insn "*adds_mul_imm_<mode>"
""
"adds\\t%<w>0, %<w>3, %<w>1, lsl %p2"
[(set_attr "v8type" "alus_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alus_shift_imm")
(set_attr "mode" "<MODE>")]
)
@@ -1381,7 +1381,7 @@ (define_insn "*subs_mul_imm_<mode>"
""
"subs\\t%<w>0, %<w>1, %<w>2, lsl %p3"
[(set_attr "v8type" "alus_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alus_shift_imm")
(set_attr "mode" "<MODE>")]
)
@@ -1397,7 +1397,7 @@ (define_insn "*adds_<optab><ALLX:mode>_<
""
"adds\\t%<GPI:w>0, %<GPI:w>2, %<GPI:w>1, <su>xt<ALLX:size>"
[(set_attr "v8type" "alus_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alus_ext")
(set_attr "mode" "<GPI:MODE>")]
)
@@ -1413,7 +1413,7 @@ (define_insn "*subs_<optab><ALLX:mode>_<
""
"subs\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size>"
[(set_attr "v8type" "alus_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alus_ext")
(set_attr "mode" "<GPI:MODE>")]
)
@@ -1435,7 +1435,7 @@ (define_insn "*adds_<optab><mode>_multp2
"aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
"adds\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
[(set_attr "v8type" "alus_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alus_ext")
(set_attr "mode" "<MODE>")]
)
@@ -1457,7 +1457,7 @@ (define_insn "*subs_<optab><mode>_multp2
"aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
"subs\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
[(set_attr "v8type" "alus_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alus_ext")
(set_attr "mode" "<MODE>")]
)
@@ -1473,7 +1473,7 @@ (define_insn "*add<mode>3nr_compare0"
cmn\\t%<w>0, %<w>1
cmp\\t%<w>0, #%n1"
[(set_attr "v8type" "alus")
- (set_attr "type" "arlo_reg,arlo_imm,arlo_imm")
+ (set_attr "type" "alus_reg,alus_imm,alus_imm")
(set_attr "mode" "<MODE>")]
)
@@ -1485,7 +1485,7 @@ (define_insn "*compare_neg<mode>"
""
"cmn\\t%<w>0, %<w>1"
[(set_attr "v8type" "alus")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alus_reg")
(set_attr "mode" "<MODE>")]
)
@@ -1497,7 +1497,7 @@ (define_insn "*add_<shift>_<mode>"
""
"add\\t%<w>0, %<w>3, %<w>1, <shift> %2"
[(set_attr "v8type" "alu_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alu_shift_imm")
(set_attr "mode" "<MODE>")]
)
@@ -1511,7 +1511,7 @@ (define_insn "*add_<shift>_si_uxtw"
""
"add\\t%w0, %w3, %w1, <shift> %2"
[(set_attr "v8type" "alu_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alu_shift_imm")
(set_attr "mode" "SI")]
)
@@ -1523,7 +1523,7 @@ (define_insn "*add_mul_imm_<mode>"
""
"add\\t%<w>0, %<w>3, %<w>1, lsl %p2"
[(set_attr "v8type" "alu_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alu_shift_imm")
(set_attr "mode" "<MODE>")]
)
@@ -1534,7 +1534,7 @@ (define_insn "*add_<optab><ALLX:mode>_<G
""
"add\\t%<GPI:w>0, %<GPI:w>2, %<GPI:w>1, <su>xt<ALLX:size>"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "<GPI:MODE>")]
)
@@ -1547,7 +1547,7 @@ (define_insn "*add_<optab><SHORT:mode>_s
""
"add\\t%w0, %w2, %w1, <su>xt<SHORT:size>"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "SI")]
)
@@ -1560,7 +1560,7 @@ (define_insn "*add_<optab><ALLX:mode>_sh
""
"add\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %2"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "<GPI:MODE>")]
)
@@ -1575,7 +1575,7 @@ (define_insn "*add_<optab><SHORT:mode>_s
""
"add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %2"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "SI")]
)
@@ -1588,7 +1588,7 @@ (define_insn "*add_<optab><ALLX:mode>_mu
""
"add\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %p2"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "<GPI:MODE>")]
)
@@ -1602,7 +1602,7 @@ (define_insn "*add_<optab><SHORT:mode>_m
""
"add\\t%w0, %w3, %w1, <su>xt<SHORT:size> %p2"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "SI")]
)
@@ -1617,7 +1617,7 @@ (define_insn "*add_<optab><mode>_multp2"
"aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
"add\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "<MODE>")]
)
@@ -1634,7 +1634,7 @@ (define_insn "*add_<optab>si_multp2_uxtw
"aarch64_is_extend_from_extract (SImode, operands[2], operands[3])"
"add\\t%w0, %w4, %w1, <su>xt%e3 %p2"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "SI")]
)
@@ -1648,7 +1648,7 @@ (define_insn "*add<mode>3_carryin"
""
"adc\\t%<w>0, %<w>1, %<w>2"
[(set_attr "v8type" "adc")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "adc_reg")
(set_attr "mode" "<MODE>")]
)
@@ -1664,7 +1664,7 @@ (define_insn "*addsi3_carryin_uxtw"
""
"adc\\t%w0, %w1, %w2"
[(set_attr "v8type" "adc")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "adc_reg")
(set_attr "mode" "SI")]
)
@@ -1678,7 +1678,7 @@ (define_insn "*add<mode>3_carryin_alt1"
""
"adc\\t%<w>0, %<w>1, %<w>2"
[(set_attr "v8type" "adc")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "adc_reg")
(set_attr "mode" "<MODE>")]
)
@@ -1694,7 +1694,7 @@ (define_insn "*addsi3_carryin_alt1_uxtw"
""
"adc\\t%w0, %w1, %w2"
[(set_attr "v8type" "adc")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "adc_reg")
(set_attr "mode" "SI")]
)
@@ -1708,7 +1708,7 @@ (define_insn "*add<mode>3_carryin_alt2"
""
"adc\\t%<w>0, %<w>1, %<w>2"
[(set_attr "v8type" "adc")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "adc_reg")
(set_attr "mode" "<MODE>")]
)
@@ -1724,7 +1724,7 @@ (define_insn "*addsi3_carryin_alt2_uxtw"
""
"adc\\t%w0, %w1, %w2"
[(set_attr "v8type" "adc")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "adc_reg")
(set_attr "mode" "SI")]
)
@@ -1738,7 +1738,7 @@ (define_insn "*add<mode>3_carryin_alt3"
""
"adc\\t%<w>0, %<w>1, %<w>2"
[(set_attr "v8type" "adc")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "adc_reg")
(set_attr "mode" "<MODE>")]
)
@@ -1754,7 +1754,7 @@ (define_insn "*addsi3_carryin_alt3_uxtw"
""
"adc\\t%w0, %w1, %w2"
[(set_attr "v8type" "adc")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "adc_reg")
(set_attr "mode" "SI")]
)
@@ -1771,7 +1771,7 @@ (define_insn "*add_uxt<mode>_multp2"
INTVAL (operands[3])));
return \"add\t%<w>0, %<w>4, %<w>1, uxt%e3 %p2\";"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "<MODE>")]
)
@@ -1790,7 +1790,7 @@ (define_insn "*add_uxtsi_multp2_uxtw"
INTVAL (operands[3])));
return \"add\t%w0, %w4, %w1, uxt%e3 %p2\";"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "SI")]
)
@@ -1801,7 +1801,7 @@ (define_insn "subsi3"
""
"sub\\t%w0, %w1, %w2"
[(set_attr "v8type" "alu")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_reg")
(set_attr "mode" "SI")]
)
@@ -1814,7 +1814,7 @@ (define_insn "*subsi3_uxtw"
""
"sub\\t%w0, %w1, %w2"
[(set_attr "v8type" "alu")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_reg")
(set_attr "mode" "SI")]
)
@@ -1827,7 +1827,7 @@ (define_insn "subdi3"
sub\\t%x0, %x1, %x2
sub\\t%d0, %d1, %d2"
[(set_attr "v8type" "alu")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_reg")
(set_attr "mode" "DI")
(set_attr "simd" "*,yes")]
)
@@ -1843,7 +1843,7 @@ (define_insn "*sub<mode>3_compare0"
""
"subs\\t%<w>0, %<w>1, %<w>2"
[(set_attr "v8type" "alus")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alus_reg")
(set_attr "mode" "<MODE>")]
)
@@ -1858,7 +1858,7 @@ (define_insn "*subsi3_compare0_uxtw"
""
"subs\\t%w0, %w1, %w2"
[(set_attr "v8type" "alus")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alus_reg")
(set_attr "mode" "SI")]
)
@@ -1871,7 +1871,7 @@ (define_insn "*sub_<shift>_<mode>"
""
"sub\\t%<w>0, %<w>3, %<w>1, <shift> %2"
[(set_attr "v8type" "alu_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alu_shift_imm")
(set_attr "mode" "<MODE>")]
)
@@ -1886,7 +1886,7 @@ (define_insn "*sub_<shift>_si_uxtw"
""
"sub\\t%w0, %w3, %w1, <shift> %2"
[(set_attr "v8type" "alu_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alu_shift_imm")
(set_attr "mode" "SI")]
)
@@ -1899,7 +1899,7 @@ (define_insn "*sub_mul_imm_<mode>"
""
"sub\\t%<w>0, %<w>3, %<w>1, lsl %p2"
[(set_attr "v8type" "alu_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alu_shift_imm")
(set_attr "mode" "<MODE>")]
)
@@ -1914,7 +1914,7 @@ (define_insn "*sub_mul_imm_si_uxtw"
""
"sub\\t%w0, %w3, %w1, lsl %p2"
[(set_attr "v8type" "alu_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alu_shift_imm")
(set_attr "mode" "SI")]
)
@@ -1926,7 +1926,7 @@ (define_insn "*sub_<optab><ALLX:mode>_<G
""
"sub\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size>"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "<GPI:MODE>")]
)
@@ -1940,7 +1940,7 @@ (define_insn "*sub_<optab><SHORT:mode>_s
""
"sub\\t%w0, %w1, %w2, <su>xt<SHORT:size>"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "SI")]
)
@@ -1953,7 +1953,7 @@ (define_insn "*sub_<optab><ALLX:mode>_sh
""
"sub\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size> %3"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "<GPI:MODE>")]
)
@@ -1968,7 +1968,7 @@ (define_insn "*sub_<optab><SHORT:mode>_s
""
"sub\\t%w0, %w1, %w2, <su>xt<SHORT:size> %3"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "SI")]
)
@@ -1983,7 +1983,7 @@ (define_insn "*sub_<optab><mode>_multp2"
"aarch64_is_extend_from_extract (<MODE>mode, operands[2], operands[3])"
"sub\\t%<w>0, %<w>4, %<w>1, <su>xt%e3 %p2"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "<MODE>")]
)
@@ -2000,7 +2000,7 @@ (define_insn "*sub_<optab>si_multp2_uxtw
"aarch64_is_extend_from_extract (SImode, operands[2], operands[3])"
"sub\\t%w0, %w4, %w1, <su>xt%e3 %p2"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "SI")]
)
@@ -2014,7 +2014,7 @@ (define_insn "*sub<mode>3_carryin"
""
"sbc\\t%<w>0, %<w>1, %<w>2"
[(set_attr "v8type" "adc")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "adc_reg")
(set_attr "mode" "<MODE>")]
)
@@ -2030,7 +2030,7 @@ (define_insn "*subsi3_carryin_uxtw"
""
"sbc\\t%w0, %w1, %w2"
[(set_attr "v8type" "adc")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "adc_reg")
(set_attr "mode" "SI")]
)
@@ -2047,7 +2047,7 @@ (define_insn "*sub_uxt<mode>_multp2"
INTVAL (operands[3])));
return \"sub\t%<w>0, %<w>4, %<w>1, uxt%e3 %p2\";"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "<MODE>")]
)
@@ -2066,7 +2066,7 @@ (define_insn "*sub_uxtsi_multp2_uxtw"
INTVAL (operands[3])));
return \"sub\t%w0, %w4, %w1, uxt%e3 %p2\";"
[(set_attr "v8type" "alu_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_ext")
(set_attr "mode" "SI")]
)
@@ -2099,7 +2099,7 @@ (define_insn_and_split "absdi2"
DONE;
}
[(set_attr "v8type" "alu")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_reg")
(set_attr "mode" "DI")]
)
@@ -2111,7 +2111,7 @@ (define_insn "neg<mode>2"
neg\\t%<w>0, %<w>1
neg\\t%<rtn>0<vas>, %<rtn>1<vas>"
[(set_attr "v8type" "alu")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_reg")
(set_attr "simd_type" "*,simd_negabs")
(set_attr "simd" "*,yes")
(set_attr "mode" "<MODE>")
@@ -2125,7 +2125,7 @@ (define_insn "*negsi2_uxtw"
""
"neg\\t%w0, %w1"
[(set_attr "v8type" "alu")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_reg")
(set_attr "mode" "SI")]
)
@@ -2136,7 +2136,7 @@ (define_insn "*ngc<mode>"
""
"ngc\\t%<w>0, %<w>1"
[(set_attr "v8type" "adc")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "adc_reg")
(set_attr "mode" "<MODE>")]
)
@@ -2148,7 +2148,7 @@ (define_insn "*ngcsi_uxtw"
""
"ngc\\t%w0, %w1"
[(set_attr "v8type" "adc")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "adc_reg")
(set_attr "mode" "SI")]
)
@@ -2161,7 +2161,7 @@ (define_insn "*neg<mode>2_compare0"
""
"negs\\t%<w>0, %<w>1"
[(set_attr "v8type" "alus")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alus_reg")
(set_attr "mode" "<MODE>")]
)
@@ -2175,7 +2175,7 @@ (define_insn "*negsi2_compare0_uxtw"
""
"negs\\t%w0, %w1"
[(set_attr "v8type" "alus")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alus_reg")
(set_attr "mode" "SI")]
)
@@ -2191,7 +2191,7 @@ (define_insn "*neg_<shift><mode>3_compar
""
"negs\\t%<w>0, %<w>1, <shift> %2"
[(set_attr "v8type" "alus_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alus_shift_imm")
(set_attr "mode" "<MODE>")]
)
@@ -2203,7 +2203,7 @@ (define_insn "*neg_<shift>_<mode>2"
""
"neg\\t%<w>0, %<w>1, <shift> %2"
[(set_attr "v8type" "alu_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alu_shift_imm")
(set_attr "mode" "<MODE>")]
)
@@ -2217,7 +2217,7 @@ (define_insn "*neg_<shift>_si2_uxtw"
""
"neg\\t%w0, %w1, <shift> %2"
[(set_attr "v8type" "alu_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alu_shift_imm")
(set_attr "mode" "SI")]
)
@@ -2229,7 +2229,7 @@ (define_insn "*neg_mul_imm_<mode>2"
""
"neg\\t%<w>0, %<w>1, lsl %p2"
[(set_attr "v8type" "alu_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alu_shift_imm")
(set_attr "mode" "<MODE>")]
)
@@ -2243,7 +2243,7 @@ (define_insn "*neg_mul_imm_si2_uxtw"
""
"neg\\t%w0, %w1, lsl %p2"
[(set_attr "v8type" "alu_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alu_shift_imm")
(set_attr "mode" "SI")]
)
@@ -2454,7 +2454,7 @@ (define_insn "*cmp<mode>"
cmp\\t%<w>0, %<w>1
cmn\\t%<w>0, #%n1"
[(set_attr "v8type" "alus")
- (set_attr "type" "arlo_reg,arlo_imm,arlo_imm")
+ (set_attr "type" "alus_reg,alus_imm,alus_imm")
(set_attr "mode" "<MODE>")]
)
@@ -2493,7 +2493,7 @@ (define_insn "*cmp_swp_<shift>_reg<mode>
""
"cmp\\t%<w>2, %<w>0, <shift> %1"
[(set_attr "v8type" "alus_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "alus_shift_imm")
(set_attr "mode" "<MODE>")]
)
@@ -2505,7 +2505,7 @@ (define_insn "*cmp_swp_<optab><ALLX:mode
""
"cmp\\t%<GPI:w>1, %<GPI:w>0, <su>xt<ALLX:size>"
[(set_attr "v8type" "alus_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alus_ext")
(set_attr "mode" "<GPI:MODE>")]
)
@@ -2519,7 +2519,7 @@ (define_insn "*cmp_swp_<optab><ALLX:mode
""
"cmp\\t%<GPI:w>2, %<GPI:w>0, <su>xt<ALLX:size> %1"
[(set_attr "v8type" "alus_ext")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alus_ext")
(set_attr "mode" "<GPI:MODE>")]
)
@@ -2560,7 +2560,7 @@ (define_insn "*cstore<mode>_insn"
""
"cset\\t%<w>0, %m1"
[(set_attr "v8type" "csel")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "csel")
(set_attr "mode" "<MODE>")]
)
@@ -2573,7 +2573,7 @@ (define_insn "*cstoresi_insn_uxtw"
""
"cset\\t%w0, %m1"
[(set_attr "v8type" "csel")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "csel")
(set_attr "mode" "SI")]
)
@@ -2584,7 +2584,7 @@ (define_insn "cstore<mode>_neg"
""
"csetm\\t%<w>0, %m1"
[(set_attr "v8type" "csel")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "csel")
(set_attr "mode" "<MODE>")]
)
@@ -2597,7 +2597,7 @@ (define_insn "*cstoresi_neg_uxtw"
""
"csetm\\t%w0, %m1"
[(set_attr "v8type" "csel")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "csel")
(set_attr "mode" "SI")]
)
@@ -2652,7 +2652,7 @@ (define_insn "*cmov<mode>_insn"
mov\\t%<w>0, -1
mov\\t%<w>0, 1"
[(set_attr "v8type" "csel")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "csel")
(set_attr "mode" "<MODE>")]
)
@@ -2677,7 +2677,7 @@ (define_insn "*cmovsi_insn_uxtw"
mov\\t%w0, -1
mov\\t%w0, 1"
[(set_attr "v8type" "csel")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "csel")
(set_attr "mode" "SI")]
)
@@ -2691,7 +2691,7 @@ (define_insn "*cmov<mode>_insn"
"TARGET_FLOAT"
"fcsel\\t%<s>0, %<s>3, %<s>4, %m1"
[(set_attr "v8type" "fcsel")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "fcsel")
(set_attr "mode" "<MODE>")]
)
@@ -2741,7 +2741,7 @@ (define_insn "*csinc2<mode>_insn"
""
"csinc\\t%<w>0, %<w>1, %<w>1, %M2"
[(set_attr "v8type" "csel")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "csel")
(set_attr "mode" "<MODE>")])
(define_insn "csinc3<mode>_insn"
@@ -2755,7 +2755,7 @@ (define_insn "csinc3<mode>_insn"
""
"csinc\\t%<w>0, %<w>4, %<w>3, %M1"
[(set_attr "v8type" "csel")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "csel")
(set_attr "mode" "<MODE>")]
)
@@ -2769,7 +2769,7 @@ (define_insn "*csinv3<mode>_insn"
""
"csinv\\t%<w>0, %<w>4, %<w>3, %M1"
[(set_attr "v8type" "csel")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "csel")
(set_attr "mode" "<MODE>")])
(define_insn "*csneg3<mode>_insn"
@@ -2782,7 +2782,7 @@ (define_insn "*csneg3<mode>_insn"
""
"csneg\\t%<w>0, %<w>4, %<w>3, %M1"
[(set_attr "v8type" "csel")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "csel")
(set_attr "mode" "<MODE>")])
;; -------------------------------------------------------------------
@@ -2796,7 +2796,7 @@ (define_insn "<optab><mode>3"
""
"<logical>\\t%<w>0, %<w>1, %<w>2"
[(set_attr "v8type" "logic,logic_imm")
- (set_attr "type" "arlo_reg,arlo_imm")
+ (set_attr "type" "logic_reg,logic_imm")
(set_attr "mode" "<MODE>")])
;; zero_extend version of above
@@ -2808,7 +2808,7 @@ (define_insn "*<optab>si3_uxtw"
""
"<logical>\\t%w0, %w1, %w2"
[(set_attr "v8type" "logic,logic_imm")
- (set_attr "type" "arlo_reg,arlo_imm")
+ (set_attr "type" "logic_reg,logic_imm")
(set_attr "mode" "SI")])
(define_insn "*and<mode>3_compare0"
@@ -2822,7 +2822,7 @@ (define_insn "*and<mode>3_compare0"
""
"ands\\t%<w>0, %<w>1, %<w>2"
[(set_attr "v8type" "logics,logics_imm")
- (set_attr "type" "arlo_reg,arlo_imm")
+ (set_attr "type" "logics_reg,logics_imm")
(set_attr "mode" "<MODE>")]
)
@@ -2838,7 +2838,7 @@ (define_insn "*andsi3_compare0_uxtw"
""
"ands\\t%w0, %w1, %w2"
[(set_attr "v8type" "logics,logics_imm")
- (set_attr "type" "arlo_reg,arlo_imm")
+ (set_attr "type" "logics_reg,logics_imm")
(set_attr "mode" "SI")]
)
@@ -2855,7 +2855,7 @@ (define_insn "*and_<SHIFT:optab><mode>3_
""
"ands\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
[(set_attr "v8type" "logics_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "logics_shift_imm")
(set_attr "mode" "<MODE>")]
)
@@ -2874,7 +2874,7 @@ (define_insn "*and_<SHIFT:optab>si3_comp
""
"ands\\t%w0, %w3, %w1, <SHIFT:shift> %2"
[(set_attr "v8type" "logics_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "logics_shift_imm")
(set_attr "mode" "SI")]
)
@@ -2887,7 +2887,7 @@ (define_insn "*<LOGICAL:optab>_<SHIFT:op
""
"<LOGICAL:logical>\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
[(set_attr "v8type" "logic_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "logic_shift_imm")
(set_attr "mode" "<MODE>")])
;; zero_extend version of above
@@ -2901,7 +2901,7 @@ (define_insn "*<LOGICAL:optab>_<SHIFT:op
""
"<LOGICAL:logical>\\t%w0, %w3, %w1, <SHIFT:shift> %2"
[(set_attr "v8type" "logic_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "logic_shift_imm")
(set_attr "mode" "SI")])
(define_insn "one_cmpl<mode>2"
@@ -2910,7 +2910,7 @@ (define_insn "one_cmpl<mode>2"
""
"mvn\\t%<w>0, %<w>1"
[(set_attr "v8type" "logic")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "logic_reg")
(set_attr "mode" "<MODE>")])
(define_insn "*one_cmpl_<optab><mode>2"
@@ -2920,7 +2920,7 @@ (define_insn "*one_cmpl_<optab><mode>2"
""
"mvn\\t%<w>0, %<w>1, <shift> %2"
[(set_attr "v8type" "logic_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "logic_shift_imm")
(set_attr "mode" "<MODE>")])
(define_insn "*<LOGICAL:optab>_one_cmpl<mode>3"
@@ -2931,7 +2931,7 @@ (define_insn "*<LOGICAL:optab>_one_cmpl<
""
"<LOGICAL:nlogical>\\t%<w>0, %<w>2, %<w>1"
[(set_attr "v8type" "logic")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "logic_reg")
(set_attr "mode" "<MODE>")])
(define_insn "*and_one_cmpl<mode>3_compare0"
@@ -2946,7 +2946,7 @@ (define_insn "*and_one_cmpl<mode>3_compa
""
"bics\\t%<w>0, %<w>2, %<w>1"
[(set_attr "v8type" "logics")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "logics_reg")
(set_attr "mode" "<MODE>")])
;; zero_extend version of above
@@ -2962,7 +2962,7 @@ (define_insn "*and_one_cmplsi3_compare0_
""
"bics\\t%w0, %w2, %w1"
[(set_attr "v8type" "logics")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "logics_reg")
(set_attr "mode" "SI")])
(define_insn "*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3"
@@ -2975,7 +2975,7 @@ (define_insn "*<LOGICAL:optab>_one_cmpl_
""
"<LOGICAL:nlogical>\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
[(set_attr "v8type" "logic_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "logics_shift_imm")
(set_attr "mode" "<MODE>")])
(define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0"
@@ -2994,7 +2994,7 @@ (define_insn "*and_one_cmpl_<SHIFT:optab
""
"bics\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
[(set_attr "v8type" "logics_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "logics_shift_imm")
(set_attr "mode" "<MODE>")])
;; zero_extend version of above
@@ -3014,7 +3014,7 @@ (define_insn "*and_one_cmpl_<SHIFT:optab
""
"bics\\t%w0, %w3, %w1, <SHIFT:shift> %2"
[(set_attr "v8type" "logics_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "logics_shift_imm")
(set_attr "mode" "SI")])
(define_insn "clz<mode>2"
@@ -3056,7 +3056,7 @@ (define_insn "rbit<mode>2"
""
"rbit\\t%<w>0, %<w>1"
[(set_attr "v8type" "rbit")
- (set_attr "type" "clz")
+ (set_attr "type" "rbit")
(set_attr "mode" "<MODE>")])
(define_expand "ctz<mode>2"
@@ -3079,7 +3079,7 @@ (define_insn "*and<mode>3nr_compare0"
""
"tst\\t%<w>0, %<w>1"
[(set_attr "v8type" "logics")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "logics_reg")
(set_attr "mode" "<MODE>")])
(define_insn "*and_<SHIFT:optab><mode>3nr_compare0"
@@ -3093,7 +3093,7 @@ (define_insn "*and_<SHIFT:optab><mode>3n
""
"tst\\t%<w>2, %<w>0, <SHIFT:shift> %1"
[(set_attr "v8type" "logics_shift")
- (set_attr "type" "arlo_shift")
+ (set_attr "type" "logics_shift_imm")
(set_attr "mode" "<MODE>")])
;; -------------------------------------------------------------------
@@ -3191,7 +3191,7 @@ (define_insn "*<optab><mode>3_insn"
""
"<shift>\\t%<w>0, %<w>1, %<w>2"
[(set_attr "v8type" "shift")
- (set_attr "type" "shift")
+ (set_attr "type" "shift_reg")
(set_attr "mode" "<MODE>")]
)
@@ -3204,7 +3204,7 @@ (define_insn "*<optab>si3_insn_uxtw"
""
"<shift>\\t%w0, %w1, %w2"
[(set_attr "v8type" "shift")
- (set_attr "type" "shift")
+ (set_attr "type" "shift_reg")
(set_attr "mode" "SI")]
)
@@ -3215,7 +3215,7 @@ (define_insn "*ashl<mode>3_insn"
""
"lsl\\t%<w>0, %<w>1, %<w>2"
[(set_attr "v8type" "shift")
- (set_attr "type" "shift")
+ (set_attr "type" "shift_reg")
(set_attr "mode" "<MODE>")]
)
@@ -3229,7 +3229,7 @@ (define_insn "*<optab><mode>3_insn"
return "<bfshift>\t%w0, %w1, %2, %3";
}
[(set_attr "v8type" "bfm")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "bfm")
(set_attr "mode" "<MODE>")]
)
@@ -3243,7 +3243,7 @@ (define_insn "*extr<mode>5_insn"
(UINTVAL (operands[3]) + UINTVAL (operands[4]) == GET_MODE_BITSIZE (<MODE>mode))"
"extr\\t%<w>0, %<w>1, %<w>2, %4"
[(set_attr "v8type" "shift")
- (set_attr "type" "shift")
+ (set_attr "type" "shift_imm")
(set_attr "mode" "<MODE>")]
)
@@ -3259,7 +3259,7 @@ (define_insn "*extrsi5_insn_uxtw"
(UINTVAL (operands[3]) + UINTVAL (operands[4]) == 32)"
"extr\\t%w0, %w1, %w2, %4"
[(set_attr "v8type" "shift")
- (set_attr "type" "shift")
+ (set_attr "type" "shift_imm")
(set_attr "mode" "SI")]
)
@@ -3273,7 +3273,7 @@ (define_insn "*ror<mode>3_insn"
return "ror\\t%<w>0, %<w>1, %3";
}
[(set_attr "v8type" "shift")
- (set_attr "type" "shift")
+ (set_attr "type" "shift_imm")
(set_attr "mode" "<MODE>")]
)
@@ -3289,7 +3289,7 @@ (define_insn "*rorsi3_insn_uxtw"
return "ror\\t%w0, %w1, %3";
}
[(set_attr "v8type" "shift")
- (set_attr "type" "shift")
+ (set_attr "type" "shift_imm")
(set_attr "mode" "SI")]
)
@@ -3304,7 +3304,7 @@ (define_insn "*<ANY_EXTEND:optab><GPI:mo
return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
[(set_attr "v8type" "bfm")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "bfm")
(set_attr "mode" "<GPI:MODE>")]
)
@@ -3319,7 +3319,7 @@ (define_insn "*zero_extend<GPI:mode>_lsh
return "ubfx\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
[(set_attr "v8type" "bfm")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "bfm")
(set_attr "mode" "<GPI:MODE>")]
)
@@ -3334,7 +3334,7 @@ (define_insn "*extend<GPI:mode>_ashr<SHO
return "sbfx\\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
[(set_attr "v8type" "bfm")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "bfm")
(set_attr "mode" "<GPI:MODE>")]
)
@@ -3359,7 +3359,7 @@ (define_insn "*<optab><mode>"
""
"<su>bfx\\t%<w>0, %<w>1, %3, %2"
[(set_attr "v8type" "bfm")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "bfm")
(set_attr "mode" "<MODE>")]
)
@@ -3404,7 +3404,7 @@ (define_insn "*insv_reg<mode>"
> GET_MODE_BITSIZE (<MODE>mode)))"
"bfi\\t%<w>0, %<w>3, %2, %1"
[(set_attr "v8type" "bfm")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "bfm")
(set_attr "mode" "<MODE>")]
)
@@ -3420,7 +3420,7 @@ (define_insn "*extr_insv_lower_reg<mode>
> GET_MODE_BITSIZE (<MODE>mode)))"
"bfxil\\t%<w>0, %<w>2, %3, %1"
[(set_attr "v8type" "bfm")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "bfm")
(set_attr "mode" "<MODE>")]
)
@@ -3437,7 +3437,7 @@ (define_insn "*<optab><ALLX:mode>_shft_<
return "<su>bfiz\t%<GPI:w>0, %<GPI:w>1, %2, %3";
}
[(set_attr "v8type" "bfm")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "bfm")
(set_attr "mode" "<GPI:MODE>")]
)
@@ -3452,7 +3452,7 @@ (define_insn "*andim_ashift<mode>_bfiz"
&& (INTVAL (operands[3]) & ((1 << INTVAL (operands[2])) - 1)) == 0"
"ubfiz\\t%<w>0, %<w>1, %2, %P3"
[(set_attr "v8type" "bfm")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "bfm")
(set_attr "mode" "<MODE>")]
)
@@ -3462,7 +3462,7 @@ (define_insn "bswap<mode>2"
""
"rev\\t%<w>0, %<w>1"
[(set_attr "v8type" "rev")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "rev")
(set_attr "mode" "<MODE>")]
)
@@ -3472,7 +3472,7 @@ (define_insn "bswaphi2"
""
"rev16\\t%w0, %w1"
[(set_attr "v8type" "rev")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "rev")
(set_attr "mode" "HI")]
)
@@ -3483,7 +3483,7 @@ (define_insn "*bswapsi2_uxtw"
""
"rev\\t%w0, %w1"
[(set_attr "v8type" "rev")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "rev")
(set_attr "mode" "SI")]
)
@@ -3938,7 +3938,7 @@ (define_insn "add_losym_<mode>"
""
"add\\t%<w>0, %<w>1, :lo12:%a2"
[(set_attr "v8type" "alu")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_reg")
(set_attr "mode" "<MODE>")]
)
@@ -4035,7 +4035,7 @@ (define_insn "tlsle_small"
""
"add\\t%0, %1, #%G2\;add\\t%0, %0, #%L2"
[(set_attr "v8type" "alu")
- (set_attr "type" "arlo_reg")
+ (set_attr "type" "alu_reg")
(set_attr "mode" "DI")
(set_attr "length" "8")]
)
diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md
index dc8e7ac8c140bd53464dfbb3d7da51e45d83b2a3..f17fa884e31b05a95f174ba7af7aa5092eaf8d98 100644
--- a/gcc/config/arm/arm-fixed.md
+++ b/gcc/config/arm/arm-fixed.md
@@ -406,7 +406,7 @@ (define_insn "arm_ssatsihi_shift"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "1")
- (set_attr "type" "arlo_shift")])
+ (set_attr "type" "alu_shift_imm")])
(define_insn "arm_usatsihi"
[(set (match_operand:HI 0 "s_register_operand" "=r")
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index d310a7c..52c0d4c 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -8664,8 +8664,14 @@ xscale_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost)
instruction we depend on is another ALU instruction, then we may
have to account for an additional stall. */
if (shift_opnum != 0
- && (attr_type == TYPE_ARLO_SHIFT
- || attr_type == TYPE_ARLO_SHIFT_REG
+ && (attr_type == TYPE_ALU_SHIFT_IMM
+ || attr_type == TYPE_ALUS_SHIFT_IMM
+ || attr_type == TYPE_LOGIC_SHIFT_IMM
+ || attr_type == TYPE_LOGICS_SHIFT_IMM
+ || attr_type == TYPE_ALU_SHIFT_REG
+ || attr_type == TYPE_ALUS_SHIFT_REG
+ || attr_type == TYPE_LOGIC_SHIFT_REG
+ || attr_type == TYPE_LOGICS_SHIFT_REG
|| attr_type == TYPE_MOV_SHIFT
|| attr_type == TYPE_MVN_SHIFT
|| attr_type == TYPE_MOV_SHIFT_REG
@@ -8952,9 +8958,17 @@ cortexa7_older_only (rtx insn)
switch (get_attr_type (insn))
{
- case TYPE_ARLO_REG:
+ case TYPE_ALU_REG:
+ case TYPE_ALUS_REG:
+ case TYPE_LOGIC_REG:
+ case TYPE_LOGICS_REG:
+ case TYPE_ADC_REG:
+ case TYPE_ADCS_REG:
+ case TYPE_ADR:
+ case TYPE_BFM:
+ case TYPE_REV:
case TYPE_MVN_REG:
- case TYPE_SHIFT:
+ case TYPE_SHIFT_IMM:
case TYPE_SHIFT_REG:
case TYPE_LOAD_BYTE:
case TYPE_LOAD1:
@@ -8999,7 +9013,10 @@ cortexa7_younger (FILE *file, int verbose, rtx insn)
switch (get_attr_type (insn))
{
- case TYPE_ARLO_IMM:
+ case TYPE_ALU_IMM:
+ case TYPE_ALUS_IMM:
+ case TYPE_LOGIC_IMM:
+ case TYPE_LOGICS_IMM:
case TYPE_EXTEND:
case TYPE_MVN_IMM:
case TYPE_MOV_IMM:
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 744f60607cbb4d31c82e81f8de2d78af97e05086..4fb12aac35bb150038b44b97275b2c028c2e482b 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -330,8 +330,12 @@ (define_attr "write_conflict" "no,yes"
; than one on the main cpu execution unit.
(define_attr "core_cycles" "single,multi"
(if_then_else (eq_attr "type"
- "arlo_imm, arlo_reg,\
- extend, shift, arlo_shift, float, fdivd, fdivs,\
+ "adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_reg,\
+ alu_shift_imm, alu_shift_reg, alus_ext, alus_imm, alus_reg,\
+ alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\
+ logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\
+ logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\
+ fdivd, fdivs,\
wmmx_wor, wmmx_wxor, wmmx_wand, wmmx_wandn, wmmx_wmov, wmmx_tmcrr,\
wmmx_tmrrc, wmmx_wldr, wmmx_wstr, wmmx_tmcr, wmmx_tmrc, wmmx_wadd,\
wmmx_wsub, wmmx_wmul, wmmx_wmac, wmmx_wavg2, wmmx_tinsr, wmmx_textrm,\
@@ -616,8 +620,8 @@ (define_insn_and_split "*arm_addsi3"
(set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no")
(set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "arlo_imm")
- (const_string "arlo_reg")))
+ (const_string "alu_imm")
+ (const_string "alu_reg")))
]
)
@@ -698,7 +702,7 @@ (define_insn "addsi3_compare0"
sub%.\\t%0, %1, #%n2
add%.\\t%0, %1, %2"
[(set_attr "conds" "set")
- (set_attr "type" "arlo_imm,arlo_imm,*")]
+ (set_attr "type" "alus_imm,alus_imm,*")]
)
(define_insn "*addsi3_compare0_scratch"
@@ -714,7 +718,7 @@ (define_insn "*addsi3_compare0_scratch"
cmn%?\\t%0, %1"
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
- (set_attr "type" "arlo_imm,arlo_imm,*")
+ (set_attr "type" "alus_imm,alus_imm,*")
]
)
@@ -804,7 +808,7 @@ (define_insn "*addsi3_compare_op1"
sub%.\\t%0, %1, #%n2
add%.\\t%0, %1, %2"
[(set_attr "conds" "set")
- (set_attr "type" "arlo_imm,arlo_imm,*")]
+ (set_attr "type" "alus_imm,alus_imm,alus_reg")]
)
(define_insn "*addsi3_compare_op2"
@@ -821,7 +825,7 @@ (define_insn "*addsi3_compare_op2"
add%.\\t%0, %1, %2
sub%.\\t%0, %1, #%n2"
[(set_attr "conds" "set")
- (set_attr "type" "arlo_imm,arlo_imm,*")]
+ (set_attr "type" "alus_imm,alus_imm,alus_reg")]
)
(define_insn "*compare_addsi2_op0"
@@ -842,7 +846,7 @@ (define_insn "*compare_addsi2_op0"
(set_attr "arch" "t2,t2,*,*,*")
(set_attr "predicable_short_it" "yes,yes,no,no,no")
(set_attr "length" "2,2,4,4,4")
- (set_attr "type" "arlo_imm,*,arlo_imm,arlo_imm,*")]
+ (set_attr "type" "alus_imm,alus_reg,alus_imm,alus_imm,alus_reg")]
)
(define_insn "*compare_addsi2_op1"
@@ -863,8 +867,7 @@ (define_insn "*compare_addsi2_op1"
(set_attr "arch" "t2,t2,*,*,*")
(set_attr "predicable_short_it" "yes,yes,no,no,no")
(set_attr "length" "2,2,4,4,4")
- (set_attr "type"
- "arlo_imm,*,arlo_imm,arlo_imm,*")]
+ (set_attr "type" "alus_imm,alus_reg,alus_imm,alus_imm,alus_reg")]
)
(define_insn "*addsi3_carryin_<optab>"
@@ -915,8 +918,8 @@ (define_insn "*addsi3_carryin_shift_<opt
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
- (const_string "arlo_shift")
- (const_string "arlo_shift_reg")))]
+ (const_string "alu_shift_imm")
+ (const_string "alu_shift_reg")))]
)
(define_insn "*addsi3_carryin_clobercc_<optab>"
@@ -994,8 +997,8 @@ (define_insn "*subsi3_carryin_shift"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
- (const_string "arlo_shift")
- (const_string "arlo_shift_reg")))]
+ (const_string "alu_shift_imm")
+ (const_string "alu_shift_reg")))]
)
(define_insn "*rsbsi3_carryin_shift"
@@ -1011,8 +1014,8 @@ (define_insn "*rsbsi3_carryin_shift"
[(set_attr "conds" "use")
(set_attr "predicable" "yes")
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
- (const_string "arlo_shift")
- (const_string "arlo_shift_reg")))]
+ (const_string "alu_shift_imm")
+ (const_string "alu_shift_reg")))]
)
; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant.
@@ -1285,7 +1288,7 @@ (define_insn_and_split "*arm_subsi3_insn
(set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no")
- (set_attr "type" "*,*,*,*,arlo_imm,arlo_imm,*,*,arlo_imm")]
+ (set_attr "type" "*,*,*,*,alu_imm,alu_imm,*,*,alu_imm")]
)
(define_peephole2
@@ -1315,7 +1318,7 @@ (define_insn "*subsi3_compare0"
sub%.\\t%0, %1, %2
rsb%.\\t%0, %2, %1"
[(set_attr "conds" "set")
- (set_attr "type" "arlo_imm,*,*")]
+ (set_attr "type" "alus_imm,alus_reg,alus_reg")]
)
(define_insn "subsi3_compare"
@@ -1330,7 +1333,7 @@ (define_insn "subsi3_compare"
sub%.\\t%0, %1, %2
rsb%.\\t%0, %2, %1"
[(set_attr "conds" "set")
- (set_attr "type" "arlo_imm,*,*")]
+ (set_attr "type" "alus_imm,alus_reg,alus_reg")]
)
(define_expand "subsf3"
@@ -2279,8 +2282,7 @@ (define_insn_and_split "*arm_andsi3_insn
[(set_attr "length" "4,4,4,4,16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no,yes,no,no,no")
- (set_attr "type"
- "arlo_imm,arlo_imm,*,*,arlo_imm")]
+ (set_attr "type" "logic_imm,logic_imm,logic_reg,logic_reg,logic_imm")]
)
(define_insn "*thumb1_andsi3_insn"
@@ -2290,7 +2292,7 @@ (define_insn "*thumb1_andsi3_insn"
"TARGET_THUMB1"
"and\\t%0, %2"
[(set_attr "length" "2")
- (set_attr "type" "arlo_imm")
+ (set_attr "type" "logic_imm")
(set_attr "conds" "set")])
(define_insn "*andsi3_compare0"
@@ -2307,7 +2309,7 @@ (define_insn "*andsi3_compare0"
bic%.\\t%0, %1, #%B2
and%.\\t%0, %1, %2"
[(set_attr "conds" "set")
- (set_attr "type" "arlo_imm,arlo_imm,*")]
+ (set_attr "type" "logics_imm,logics_imm,logics_reg")]
)
(define_insn "*andsi3_compare0_scratch"
@@ -2323,7 +2325,7 @@ (define_insn "*andsi3_compare0_scratch"
bic%.\\t%2, %0, #%B1
tst%?\\t%0, %1"
[(set_attr "conds" "set")
- (set_attr "type" "arlo_imm,arlo_imm,*")]
+ (set_attr "type" "logics_imm,logics_imm,logics_reg")]
)
(define_insn "*zeroextractsi_compare0_scratch"
@@ -2347,7 +2349,7 @@ (define_insn "*zeroextractsi_compare0_sc
[(set_attr "conds" "set")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "type" "arlo_imm")]
+ (set_attr "type" "logics_imm")]
)
(define_insn_and_split "*ne_zeroextractsi"
@@ -2775,7 +2777,8 @@ (define_insn "insv_zero"
"bfc%?\t%0, %2, %1"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "bfm")]
)
(define_insn "insv_t2"
@@ -2787,7 +2790,8 @@ (define_insn "insv_t2"
"bfi%?\t%0, %3, %2, %1"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "bfm")]
)
; constants for op 2 will never be given to these patterns.
@@ -2897,8 +2901,8 @@ (define_insn "andsi_not_shiftsi_si"
[(set_attr "predicable" "yes")
(set_attr "shift" "2")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "arlo_shift")
- (const_string "arlo_shift_reg")))]
+ (const_string "logic_shift_imm")
+ (const_string "logic_shift_reg")))]
)
(define_insn "*andsi_notsi_si_compare0"
@@ -2911,7 +2915,8 @@ (define_insn "*andsi_notsi_si_compare0"
(and:SI (not:SI (match_dup 2)) (match_dup 1)))]
"TARGET_32BIT"
"bic%.\\t%0, %1, %2"
- [(set_attr "conds" "set")]
+ [(set_attr "conds" "set")
+ (set_attr "type" "logics_shift_reg")]
)
(define_insn "*andsi_notsi_si_compare0_scratch"
@@ -2923,7 +2928,8 @@ (define_insn "*andsi_notsi_si_compare0_s
(clobber (match_scratch:SI 0 "=r"))]
"TARGET_32BIT"
"bic%.\\t%0, %1, %2"
- [(set_attr "conds" "set")]
+ [(set_attr "conds" "set")
+ (set_attr "type" "logics_shift_reg")]
)
(define_expand "iordi3"
@@ -3057,7 +3063,7 @@ (define_insn_and_split "*iorsi3_insn"
(set_attr "arch" "32,t2,t2,32,32")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no,yes,no,no,no")
- (set_attr "type" "arlo_imm,*,arlo_imm,*,*")]
+ (set_attr "type" "logic_imm,logic_reg,logic_imm,logic_reg,logic_reg")]
)
(define_insn "*thumb1_iorsi3_insn"
@@ -3092,7 +3098,7 @@ (define_insn "*iorsi3_compare0"
"TARGET_32BIT"
"orr%.\\t%0, %1, %2"
[(set_attr "conds" "set")
- (set_attr "type" "arlo_imm,*")]
+ (set_attr "type" "logics_imm,logics_reg")]
)
(define_insn "*iorsi3_compare0_scratch"
@@ -3104,7 +3110,7 @@ (define_insn "*iorsi3_compare0_scratch"
"TARGET_32BIT"
"orr%.\\t%0, %1, %2"
[(set_attr "conds" "set")
- (set_attr "type" "arlo_imm,*")]
+ (set_attr "type" "logics_imm,logics_reg")]
)
(define_expand "xordi3"
@@ -3230,7 +3236,7 @@ (define_insn_and_split "*arm_xorsi3"
[(set_attr "length" "4,4,4,16")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no,yes,no,no")
- (set_attr "type" "arlo_imm,*,*,*")]
+ (set_attr "type" "logic_imm,logic_reg,logic_reg,logic_reg")]
)
(define_insn "*thumb1_xorsi3_insn"
@@ -3241,7 +3247,7 @@ (define_insn "*thumb1_xorsi3_insn"
"eor\\t%0, %2"
[(set_attr "length" "2")
(set_attr "conds" "set")
- (set_attr "type" "arlo_imm")]
+ (set_attr "type" "logics_reg")]
)
(define_insn "*xorsi3_compare0"
@@ -3254,7 +3260,7 @@ (define_insn "*xorsi3_compare0"
"TARGET_32BIT"
"eor%.\\t%0, %1, %2"
[(set_attr "conds" "set")
- (set_attr "type" "arlo_imm,*")]
+ (set_attr "type" "logics_imm,logics_reg")]
)
(define_insn "*xorsi3_compare0_scratch"
@@ -3265,7 +3271,7 @@ (define_insn "*xorsi3_compare0_scratch"
"TARGET_32BIT"
"teq%?\\t%0, %1"
[(set_attr "conds" "set")
- (set_attr "type" "arlo_imm,*")]
+ (set_attr "type" "logics_imm,logics_reg")]
)
; By splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C),
@@ -3754,7 +3760,7 @@ (define_insn "*satsi_<SAT:code>_shift"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "3")
- (set_attr "type" "arlo_shift")])
+ (set_attr "type" "logic_shift_reg")])
;; Shift and rotation insns
@@ -3857,7 +3863,7 @@ (define_insn "*thumb1_ashlsi3"
"TARGET_THUMB1"
"lsl\\t%0, %1, %2"
[(set_attr "length" "2")
- (set_attr "type" "shift,shift_reg")
+ (set_attr "type" "shift_imm,shift_reg")
(set_attr "conds" "set")])
(define_expand "ashrdi3"
@@ -3962,7 +3968,7 @@ (define_insn "*thumb1_ashrsi3"
"TARGET_THUMB1"
"asr\\t%0, %1, %2"
[(set_attr "length" "2")
- (set_attr "type" "shift,shift_reg")
+ (set_attr "type" "shift_imm,shift_reg")
(set_attr "conds" "set")])
(define_expand "lshrdi3"
@@ -4059,7 +4065,7 @@ (define_insn "*thumb1_lshrsi3"
"TARGET_THUMB1"
"lsr\\t%0, %1, %2"
[(set_attr "length" "2")
- (set_attr "type" "shift,shift_reg")
+ (set_attr "type" "shift_imm,shift_reg")
(set_attr "conds" "set")])
(define_expand "rotlsi3"
@@ -4121,7 +4127,7 @@ (define_insn "*arm_shiftsi3"
(set_attr "predicable_short_it" "yes,no,no")
(set_attr "length" "4")
(set_attr "shift" "1")
- (set_attr "type" "arlo_shift_reg,arlo_shift,arlo_shift_reg")]
+ (set_attr "type" "alu_shift_reg,alu_shift_imm,alu_shift_reg")]
)
(define_insn "*shiftsi3_compare"
@@ -4136,7 +4142,7 @@ (define_insn "*shiftsi3_compare"
"* return arm_output_shift(operands, 1);"
[(set_attr "conds" "set")
(set_attr "shift" "1")
- (set_attr "type" "arlo_shift,arlo_shift_reg")]
+ (set_attr "type" "alus_shift_imm,alus_shift_reg")]
)
(define_insn "*shiftsi3_compare0"
@@ -4151,7 +4157,7 @@ (define_insn "*shiftsi3_compare0"
"* return arm_output_shift(operands, 1);"
[(set_attr "conds" "set")
(set_attr "shift" "1")
- (set_attr "type" "arlo_shift,arlo_shift_reg")]
+ (set_attr "type" "alus_shift_imm,alus_shift_reg")]
)
(define_insn "*shiftsi3_compare0_scratch"
@@ -4165,7 +4171,7 @@ (define_insn "*shiftsi3_compare0_scratch
"* return arm_output_shift(operands, 1);"
[(set_attr "conds" "set")
(set_attr "shift" "1")
- (set_attr "type" "shift,shift_reg")]
+ (set_attr "type" "shift_imm,shift_reg")]
)
(define_insn "*not_shiftsi"
@@ -4507,7 +4513,8 @@ (define_insn "*extv_reg"
"sbfx%?\t%0, %1, %3, %2"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "bfm")]
)
(define_insn "extzv_t2"
@@ -4519,7 +4526,8 @@ (define_insn "extzv_t2"
"ubfx%?\t%0, %1, %3, %2"
[(set_attr "length" "4")
(set_attr "predicable" "yes")
- (set_attr "predicable_short_it" "no")]
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "bfm")]
)
@@ -5241,7 +5249,7 @@ (define_insn "*arm_zero_extendhisi2"
"@
#
ldr%(h%)\\t%0, %1"
- [(set_attr "type" "arlo_shift,load_byte")
+ [(set_attr "type" "alu_shift_reg,load_byte")
(set_attr "predicable" "yes")]
)
@@ -5262,7 +5270,7 @@ (define_insn "*arm_zero_extendhisi2addsi
(match_operand:SI 2 "s_register_operand" "r")))]
"TARGET_INT_SIMD"
"uxtah%?\\t%0, %2, %1"
- [(set_attr "type" "arlo_shift")
+ [(set_attr "type" "alu_shift_reg")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
)
@@ -5312,7 +5320,7 @@ (define_insn "*thumb1_zero_extendqisi2"
#
ldrb\\t%0, %1"
[(set_attr "length" "4,2")
- (set_attr "type" "arlo_shift,load_byte")
+ (set_attr "type" "alu_shift_reg,load_byte")
(set_attr "pool_range" "*,32")]
)
@@ -5335,7 +5343,7 @@ (define_insn "*arm_zero_extendqisi2"
#
ldr%(b%)\\t%0, %1\\t%@ zero_extendqisi2"
[(set_attr "length" "8,4")
- (set_attr "type" "arlo_shift,load_byte")
+ (set_attr "type" "alu_shift_reg,load_byte")
(set_attr "predicable" "yes")]
)
@@ -5358,7 +5366,7 @@ (define_insn "*arm_zero_extendqisi2addsi
"uxtab%?\\t%0, %2, %1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
- (set_attr "type" "arlo_shift")]
+ (set_attr "type" "alu_shift_reg")]
)
(define_split
@@ -5580,7 +5588,7 @@ (define_insn "*arm_extendhisi2"
#
ldr%(sh%)\\t%0, %1"
[(set_attr "length" "8,4")
- (set_attr "type" "arlo_shift,load_byte")
+ (set_attr "type" "alu_shift_reg,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,256")
(set_attr "neg_pool_range" "*,244")]
@@ -5681,7 +5689,7 @@ (define_insn "*arm_extendqisi"
#
ldr%(sb%)\\t%0, %1"
[(set_attr "length" "8,4")
- (set_attr "type" "arlo_shift,load_byte")
+ (set_attr "type" "alu_shift_reg,load_byte")
(set_attr "predicable" "yes")
(set_attr "pool_range" "*,256")
(set_attr "neg_pool_range" "*,244")]
@@ -5707,7 +5715,7 @@ (define_insn "*arm_extendqisi2addsi"
(match_operand:SI 2 "s_register_operand" "r")))]
"TARGET_INT_SIMD"
"sxtab%?\\t%0, %2, %1"
- [(set_attr "type" "arlo_shift")
+ [(set_attr "type" "alu_shift_reg")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")]
)
@@ -6484,7 +6492,7 @@ (define_insn "*movsi_compare0"
cmp%?\\t%0, #0
sub%.\\t%0, %1, #0"
[(set_attr "conds" "set")
- (set_attr "type" "arlo_imm,arlo_imm")]
+ (set_attr "type" "alus_imm,alus_imm")]
)
;; Subroutine to store a half word from a register into memory.
@@ -7078,7 +7086,7 @@ (define_insn "*thumb1_movqi_insn"
mov\\t%0, %1
mov\\t%0, %1"
[(set_attr "length" "2")
- (set_attr "type" "arlo_imm,load1,store1,mov_reg,mov_imm,mov_imm")
+ (set_attr "type" "alu_imm,load1,store1,mov_reg,mov_imm,mov_imm")
(set_attr "pool_range" "*,32,*,*,*,*")
(set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob")])
@@ -8164,34 +8172,34 @@ (define_insn "*arm_cmpsi_insn"
(set_attr "arch" "t2,t2,any,any")
(set_attr "length" "2,2,4,4")
(set_attr "predicable" "yes")
- (set_attr "type" "*,*,*,arlo_imm")]
+ (set_attr "type" "alus_reg,alus_reg,alus_reg,alus_imm")]
)
(define_insn "*cmpsi_shiftsi"
[(set (reg:CC CC_REGNUM)
- (compare:CC (match_operand:SI 0 "s_register_operand" "r,r")
+ (compare:CC (match_operand:SI 0 "s_register_operand" "r,r,r")
(match_operator:SI 3 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r,r")
- (match_operand:SI 2 "shift_amount_operand" "M,rM")])))]
+ [(match_operand:SI 1 "s_register_operand" "r,r,r")
+ (match_operand:SI 2 "shift_amount_operand" "M,r,M")])))]
"TARGET_32BIT"
"cmp%?\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
- (set_attr "arch" "32,a")
- (set_attr "type" "arlo_shift,arlo_shift_reg")])
+ (set_attr "arch" "32,a,a")
+ (set_attr "type" "alus_shift_imm,alu_shift_reg,alus_shift_imm")])
(define_insn "*cmpsi_shiftsi_swp"
[(set (reg:CC_SWP CC_REGNUM)
(compare:CC_SWP (match_operator:SI 3 "shift_operator"
- [(match_operand:SI 1 "s_register_operand" "r,r")
- (match_operand:SI 2 "shift_amount_operand" "M,rM")])
- (match_operand:SI 0 "s_register_operand" "r,r")))]
+ [(match_operand:SI 1 "s_register_operand" "r,r,r")
+ (match_operand:SI 2 "shift_amount_operand" "M,r,M")])
+ (match_operand:SI 0 "s_register_operand" "r,r,r")))]
"TARGET_32BIT"
"cmp%?\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
- (set_attr "arch" "32,a")
- (set_attr "type" "arlo_shift,arlo_shift_reg")])
+ (set_attr "arch" "32,a,a")
+ (set_attr "type" "alus_shift_imm,alu_shift_reg,alus_shift_imm")])
(define_insn "*arm_cmpsi_negshiftsi_si"
[(set (reg:CC_Z CC_REGNUM)
@@ -8204,8 +8212,8 @@ (define_insn "*arm_cmpsi_negshiftsi_si"
"cmn%?\\t%0, %2%S1"
[(set_attr "conds" "set")
(set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "arlo_shift")
- (const_string "arlo_shift_reg")))
+ (const_string "alus_shift_imm")
+ (const_string "alus_shift_reg")))
(set_attr "predicable" "yes")]
)
@@ -9747,7 +9755,7 @@ (define_insn "*arith_shiftsi"
(if_then_else
(match_operand:SI 3 "mult_operator" "")
(const_string "no") (const_string "yes"))])
- (set_attr "type" "arlo_shift,arlo_shift,arlo_shift,arlo_shift_reg")])
+ (set_attr "type" "alu_shift_imm,alu_shift_imm,alu_shift_imm,alu_shift_reg")])
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
@@ -9784,7 +9792,7 @@ (define_insn "*arith_shiftsi_compare0"
[(set_attr "conds" "set")
(set_attr "shift" "4")
(set_attr "arch" "32,a")
- (set_attr "type" "arlo_shift,arlo_shift_reg")])
+ (set_attr "type" "alus_shift_imm,alus_shift_reg")])
(define_insn "*arith_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
@@ -9801,7 +9809,7 @@ (define_insn "*arith_shiftsi_compare0_sc
[(set_attr "conds" "set")
(set_attr "shift" "4")
(set_attr "arch" "32,a")
- (set_attr "type" "arlo_shift,arlo_shift_reg")])
+ (set_attr "type" "alus_shift_imm,alus_shift_reg")])
(define_insn "*sub_shiftsi"
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
@@ -9814,41 +9822,41 @@ (define_insn "*sub_shiftsi"
[(set_attr "predicable" "yes")
(set_attr "shift" "3")
(set_attr "arch" "32,a")
- (set_attr "type" "arlo_shift,arlo_shift_reg")])
+ (set_attr "type" "alus_shift_imm,alus_shift_reg")])
(define_insn "*sub_shiftsi_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
- (minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
+ (minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
(match_operator:SI 2 "shift_operator"
- [(match_operand:SI 3 "s_register_operand" "r,r")
- (match_operand:SI 4 "shift_amount_operand" "M,rM")]))
+ [(match_operand:SI 3 "s_register_operand" "r,r,r")
+ (match_operand:SI 4 "shift_amount_operand" "M,r,M")]))
(const_int 0)))
- (set (match_operand:SI 0 "s_register_operand" "=r,r")
+ (set (match_operand:SI 0 "s_register_operand" "=r,r,r")
(minus:SI (match_dup 1)
(match_op_dup 2 [(match_dup 3) (match_dup 4)])))]
"TARGET_32BIT"
"sub%.\\t%0, %1, %3%S2"
[(set_attr "conds" "set")
(set_attr "shift" "3")
- (set_attr "arch" "32,a")
- (set_attr "type" "arlo_shift,arlo_shift_reg")])
+ (set_attr "arch" "32,a,a")
+ (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
(define_insn "*sub_shiftsi_compare0_scratch"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV
- (minus:SI (match_operand:SI 1 "s_register_operand" "r,r")
+ (minus:SI (match_operand:SI 1 "s_register_operand" "r,r,r")
(match_operator:SI 2 "shift_operator"
- [(match_operand:SI 3 "s_register_operand" "r,r")
- (match_operand:SI 4 "shift_amount_operand" "M,rM")]))
+ [(match_operand:SI 3 "s_register_operand" "r,r,r")
+ (match_operand:SI 4 "shift_amount_operand" "M,r,M")]))
(const_int 0)))
- (clobber (match_scratch:SI 0 "=r,r"))]
+ (clobber (match_scratch:SI 0 "=r,r,r"))]
"TARGET_32BIT"
"sub%.\\t%0, %1, %3%S2"
[(set_attr "conds" "set")
(set_attr "shift" "3")
- (set_attr "arch" "32,a")
- (set_attr "type" "arlo_shift,arlo_shift_reg")])
+ (set_attr "arch" "32,a,a")
+ (set_attr "type" "alus_shift_imm,alus_shift_reg,alus_shift_imm")])
(define_insn_and_split "*and_scc"
@@ -10900,9 +10908,9 @@ (define_insn "*if_plus_move"
(set_attr "length" "4,4,8,8")
(set_attr_alternative "type"
[(if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "arlo_imm" )
+ (const_string "alu_imm" )
(const_string "*"))
- (const_string "arlo_imm")
+ (const_string "alu_imm")
(const_string "*")
(const_string "*")])]
)
@@ -10942,9 +10950,9 @@ (define_insn "*if_move_plus"
(set_attr "length" "4,4,8,8")
(set_attr_alternative "type"
[(if_then_else (match_operand 3 "const_int_operand" "")
- (const_string "arlo_imm" )
+ (const_string "alu_imm" )
(const_string "*"))
- (const_string "arlo_imm")
+ (const_string "alu_imm")
(const_string "*")
(const_string "*")])]
)
diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md
index 3a5e08fb7e5c079afa6e769e11d569bef30784ce..ce89f1db02acf1cc36a097423f3c7e9f2be3e898 100644
--- a/gcc/config/arm/arm1020e.md
+++ b/gcc/config/arm/arm1020e.md
@@ -66,14 +66,20 @@ (define_cpu_unit "1020l_e,1020l_m,1020l_
;; ALU operations with no shifted operand
(define_insn_reservation "1020alu_op" 1
(and (eq_attr "tune" "arm1020e,arm1022e")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"1020a_e,1020a_m,1020a_w")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "1020alu_shift_op" 1
(and (eq_attr "tune" "arm1020e,arm1022e")
- (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
+ (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ extend,mov_shift,mvn_shift"))
"1020a_e,1020a_m,1020a_w")
;; ALU operations with a shift-by-register operand
@@ -82,7 +88,9 @@ (define_insn_reservation "1020alu_shift_
;; the execute stage.
(define_insn_reservation "1020alu_shift_reg_op" 2
(and (eq_attr "tune" "arm1020e,arm1022e")
- (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
+ (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
+ mov_shift_reg,mvn_shift_reg"))
"1020a_e*2,1020a_m,1020a_w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff --git a/gcc/config/arm/arm1026ejs.md b/gcc/config/arm/arm1026ejs.md
index 9112122d67b5b13189fe4e936b2c9775117ca191..6f4a8fa76e1d26f6d6e61ba2c6963dd8aa46194f 100644
--- a/gcc/config/arm/arm1026ejs.md
+++ b/gcc/config/arm/arm1026ejs.md
@@ -66,14 +66,20 @@ (define_cpu_unit "l_e,l_m,l_w" "arm1026e
;; ALU operations with no shifted operand
(define_insn_reservation "alu_op" 1
(and (eq_attr "tune" "arm1026ejs")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"a_e,a_m,a_w")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "alu_shift_op" 1
(and (eq_attr "tune" "arm1026ejs")
- (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
+ (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ extend,mov_shift,mvn_shift"))
"a_e,a_m,a_w")
;; ALU operations with a shift-by-register operand
@@ -82,7 +88,9 @@ (define_insn_reservation "alu_shift_op"
;; the execute stage.
(define_insn_reservation "alu_shift_reg_op" 2
(and (eq_attr "tune" "arm1026ejs")
- (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
+ (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
+ mov_shift_reg,mvn_shift_reg"))
"a_e*2,a_m,a_w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff --git a/gcc/config/arm/arm1136jfs.md b/gcc/config/arm/arm1136jfs.md
index f83b9d14f2b72d09530163138a73fb8ae35e77ef..7d39f12d08a7d5f558e0bcaf0dca5d5effe07946 100644
--- a/gcc/config/arm/arm1136jfs.md
+++ b/gcc/config/arm/arm1136jfs.md
@@ -75,14 +75,20 @@ (define_cpu_unit "l_a,l_dc1,l_dc2,l_wb"
;; ALU operations with no shifted operand
(define_insn_reservation "11_alu_op" 2
(and (eq_attr "tune" "arm1136js,arm1136jfs")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"e_1,e_2,e_3,e_wb")
;; ALU operations with a shift-by-constant operand
(define_insn_reservation "11_alu_shift_op" 2
(and (eq_attr "tune" "arm1136js,arm1136jfs")
- (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
+ (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ extend,mov_shift,mvn_shift"))
"e_1,e_2,e_3,e_wb")
;; ALU operations with a shift-by-register operand
@@ -91,7 +97,9 @@ (define_insn_reservation "11_alu_shift_o
;; the shift stage.
(define_insn_reservation "11_alu_shift_reg_op" 3
(and (eq_attr "tune" "arm1136js,arm1136jfs")
- (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
+ (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
+ mov_shift_reg,mvn_shift_reg"))
"e_1*2,e_2,e_3,e_wb")
;; alu_ops can start sooner, if there is no shifter dependency
diff --git a/gcc/config/arm/arm926ejs.md b/gcc/config/arm/arm926ejs.md
index 8c38e86ce667de26013dc4ab8e39a59c13df0d8b..7c2d52e80739d2bcbceb0cb1ce65444162c23b12 100644
--- a/gcc/config/arm/arm926ejs.md
+++ b/gcc/config/arm/arm926ejs.md
@@ -58,7 +58,13 @@ (define_cpu_unit "e,m,w" "arm926ejs")
;; ALU operations with no shifted operand
(define_insn_reservation "9_alu_op" 1
(and (eq_attr "tune" "arm926ejs")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,arlo_shift,\
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ shift_imm,shift_reg,extend,\
mov_imm,mov_reg,mov_shift,\
mvn_imm,mvn_reg,mvn_shift"))
"e,m,w")
@@ -69,7 +75,9 @@ (define_insn_reservation "9_alu_op" 1
;; the execute stage.
(define_insn_reservation "9_alu_shift_reg_op" 2
(and (eq_attr "tune" "arm926ejs")
- (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
+ (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
+ mov_shift_reg,mvn_shift_reg"))
"e*2,m,w")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md
index a816e29a3cbde6eb1859f266bf662a5d71584ec1..382a3dc73d48b003edec15e6b14e2c1690b41314 100644
--- a/gcc/config/arm/cortex-a15.md
+++ b/gcc/config/arm/cortex-a15.md
@@ -61,22 +61,31 @@ (define_cpu_unit "ca15_sx2_alu, ca15_sx2
;; Simple ALU without shift
(define_insn_reservation "cortex_a15_alu" 2
(and (eq_attr "tune" "cortexa15")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
- mov_imm,mov_reg,\
- mvn_imm,mvn_reg"))
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg,\
+ mov_imm,mov_reg,\
+ mvn_imm,mvn_reg"))
"ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
;; ALU ops with immediate shift
(define_insn_reservation "cortex_a15_alu_shift" 3
(and (eq_attr "tune" "cortexa15")
- (eq_attr "type" "extend,arlo_shift,,mov_shift,mvn_shift"))
+ (eq_attr "type" "extend,\
+ alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ mov_shift,mvn_shift"))
"ca15_issue1,(ca15_sx1,ca15_sx1+ca15_sx1_shf,ca15_sx1_alu)\
|(ca15_sx2,ca15_sx2+ca15_sx2_shf,ca15_sx2_alu)")
;; ALU ops with register controlled shift
(define_insn_reservation "cortex_a15_alu_shift_reg" 3
(and (eq_attr "tune" "cortexa15")
- (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
+ (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
+ mov_shift_reg,mvn_shift_reg"))
"(ca15_issue2,ca15_sx1+ca15_sx2,ca15_sx1_shf,ca15_sx2_alu)\
|(ca15_issue1,(ca15_issue1+ca15_sx2,ca15_sx1+ca15_sx2_shf)\
|(ca15_issue1+ca15_sx1,ca15_sx1+ca15_sx1_shf),ca15_sx1_alu)")
diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md
index 67f641c174bc9e3f4379f0b0709ce6ddafab2378..19738e6d56f58f4516490244f2d6b9ea202f67a3 100644
--- a/gcc/config/arm/cortex-a5.md
+++ b/gcc/config/arm/cortex-a5.md
@@ -58,13 +58,21 @@ (define_cpu_unit "cortex_a5_fp_div_sqrt"
(define_insn_reservation "cortex_a5_alu" 2
(and (eq_attr "tune" "cortexa5")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"cortex_a5_ex1")
(define_insn_reservation "cortex_a5_alu_shift" 2
(and (eq_attr "tune" "cortexa5")
- (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
+ (eq_attr "type" "extend,\
+ alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"cortex_a5_ex1")
diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md
index 5bb8ab02a331eff598bb1debc28d1f389a593d1c..9331eceb2ed7e2094f7ec1ba04ba6396fbd8e912 100644
--- a/gcc/config/arm/cortex-a53.md
+++ b/gcc/config/arm/cortex-a53.md
@@ -67,13 +67,20 @@ (define_cpu_unit "cortex_a53_fp_div_sqrt
(define_insn_reservation "cortex_a53_alu" 2
(and (eq_attr "tune" "cortexa53")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,csel,rev,\
+ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"cortex_a53_slot_any")
(define_insn_reservation "cortex_a53_alu_shift" 2
(and (eq_attr "tune" "cortexa53")
- (eq_attr "type" "arlo_shift,arlo_shift_reg,\
+ (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"cortex_a53_slot_any")
@@ -202,7 +209,7 @@ (define_insn_reservation "cortex_a53_bra
(define_insn_reservation "cortex_a53_fpalu" 4
(and (eq_attr "tune" "cortexa53")
(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
- fcmps, fcmpd"))
+ fcmps, fcmpd, fcsel"))
"cortex_a53_slot0+cortex_a53_fpadd_pipe")
(define_insn_reservation "cortex_a53_fconst" 2
diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md
index cb1f7cff2642e83d058ee75d6b67461982523c45..9373077b754eaca1aacf0c468b9295e6d183164f 100644
--- a/gcc/config/arm/cortex-a7.md
+++ b/gcc/config/arm/cortex-a7.md
@@ -86,7 +86,8 @@ (define_insn_reservation "cortex_a7_call
;; ALU instruction with an immediate operand can dual-issue.
(define_insn_reservation "cortex_a7_alu_imm" 2
(and (eq_attr "tune" "cortexa7")
- (ior (eq_attr "type" "arlo_imm,mov_imm,mvn_imm,extend")
+ (ior (eq_attr "type" "adr,alu_imm,alus_imm,logic_imm,logics_imm,\
+ mov_imm,mvn_imm,extend")
(and (eq_attr "type" "mov_reg,mov_shift,mov_shift_reg")
(not (eq_attr "length" "8")))))
"cortex_a7_ex2|cortex_a7_ex1")
@@ -95,12 +96,18 @@ (define_insn_reservation "cortex_a7_alu_
;; with a younger immediate-based instruction.
(define_insn_reservation "cortex_a7_alu_reg" 2
(and (eq_attr "tune" "cortexa7")
- (eq_attr "type" "arlo_reg,shift,shift_reg,mov_reg,mvn_reg"))
+ (eq_attr "type" "alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ bfm,rev,\
+ shift_imm,shift_reg,mov_reg,mvn_reg"))
"cortex_a7_ex1")
(define_insn_reservation "cortex_a7_alu_shift" 2
(and (eq_attr "tune" "cortexa7")
- (eq_attr "type" "arlo_shift,arlo_shift_reg,\
+ (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"cortex_a7_ex1")
diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md
index acbfef587b0c98a33a089ef70dc77ee1c76d825f..22f9ee92bdecc006bf74beec8d06ef8424dcb14d 100644
--- a/gcc/config/arm/cortex-a8.md
+++ b/gcc/config/arm/cortex-a8.md
@@ -85,17 +85,24 @@ (define_reservation "cortex_a8_multiply_
;; (source read in E2 and destination available at the end of that cycle).
(define_insn_reservation "cortex_a8_alu" 2
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,clz"))
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,clz,rbit,rev,\
+ shift_imm,shift_reg"))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift" 2
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "extend,arlo_shift"))
+ (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ extend"))
"cortex_a8_default")
(define_insn_reservation "cortex_a8_alu_shift_reg" 2
(and (eq_attr "tune" "cortexa8")
- (eq_attr "type" "arlo_shift_reg"))
+ (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg"))
"cortex_a8_default")
;; Move instructions.
diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md
index 198e8de80cfe46dff253bf720812b41bb1446c54..e5788b6b872020a651d06fcd28e834b44e500e64 100644
--- a/gcc/config/arm/cortex-a9.md
+++ b/gcc/config/arm/cortex-a9.md
@@ -80,7 +80,11 @@ (define_reservation "cortex_a9_mult_long
;; which can go down E2 without any problem.
(define_insn_reservation "cortex_a9_dp" 2
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg,\
mov_shift_reg,mov_shift"))
"cortex_a9_p0_default|cortex_a9_p1_default")
@@ -88,8 +92,11 @@ (define_insn_reservation "cortex_a9_dp"
;; An instruction using the shifter will go down E1.
(define_insn_reservation "cortex_a9_dp_shift" 3
(and (eq_attr "tune" "cortexa9")
- (eq_attr "type" "arlo_shift_reg,extend,arlo_shift,\
- mvn_shift,mvn_shift_reg"))
+ (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
+ extend,mvn_shift,mvn_shift_reg"))
"cortex_a9_p0_shift | cortex_a9_p1_shift")
;; Loads have a latency of 4 cycles.
diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md
index 53bd60cd98f66c6f51e68bb69ffaa722df03fd51..0c628f08b5f6dcbe326b0caeb650ae2464fa4cb9 100644
--- a/gcc/config/arm/cortex-m4.md
+++ b/gcc/config/arm/cortex-m4.md
@@ -31,8 +31,15 @@ (define_reservation "cortex_m4_ex" "cort
;; ALU and multiply is one cycle.
(define_insn_reservation "cortex_m4_alu" 1
(and (eq_attr "tune" "cortexm4")
- (ior (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,extend,\
- arlo_shift,arlo_shift_reg,\
+ (ior (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg,extend,\
+ alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
mov_imm,mov_reg,mov_shift,mov_shift_reg,\
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")
(ior (eq_attr "mul32" "yes")
diff --git a/gcc/config/arm/cortex-r4.md b/gcc/config/arm/cortex-r4.md
index 597774dbd89d766921c4f050211b567a1ceefa0a..83745c1b4c7beaed1f9e8e200f696d7c6f67512e 100644
--- a/gcc/config/arm/cortex-r4.md
+++ b/gcc/config/arm/cortex-r4.md
@@ -78,7 +78,11 @@ (define_reservation "cortex_r4_branch" "
;; for the purposes of the dual-issue constraints above.
(define_insn_reservation "cortex_r4_alu" 2
(and (eq_attr "tune_cortexr4" "yes")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,mvn_imm,mvn_reg"))
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg,mvn_imm,mvn_reg"))
"cortex_r4_alu")
(define_insn_reservation "cortex_r4_mov" 2
@@ -88,12 +92,16 @@ (define_insn_reservation "cortex_r4_mov"
(define_insn_reservation "cortex_r4_alu_shift" 2
(and (eq_attr "tune_cortexr4" "yes")
- (eq_attr "type" "extend,arlo_shift,mov_shift,mvn_shift"))
+ (eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ extend,mov_shift,mvn_shift"))
"cortex_r4_alu")
(define_insn_reservation "cortex_r4_alu_shift_reg" 2
(and (eq_attr "tune_cortexr4" "yes")
- (eq_attr "type" "arlo_shift_reg,mov_shift_reg,mvn_shift_reg"))
+ (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
+ mov_shift_reg,mvn_shift_reg"))
"cortex_r4_alu_shift_reg")
;; An ALU instruction followed by an ALU instruction with no early dep.
diff --git a/gcc/config/arm/fa526.md b/gcc/config/arm/fa526.md
index 9ec92d60dc5a6017a76db881e7e165120d149af8..90abf6cb85917008901fdc261aaea89d5f2940e1 100644
--- a/gcc/config/arm/fa526.md
+++ b/gcc/config/arm/fa526.md
@@ -62,13 +62,21 @@ (define_cpu_unit "fa526_core" "fa526")
;; ALU operations
(define_insn_reservation "526_alu_op" 1
(and (eq_attr "tune" "fa526")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"fa526_core")
(define_insn_reservation "526_alu_shift_op" 2
(and (eq_attr "tune" "fa526")
- (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
+ (eq_attr "type" "extend,\
+ alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"fa526_core")
diff --git a/gcc/config/arm/fa606te.md b/gcc/config/arm/fa606te.md
index e61242886d7bd154639e1be00b2b20a74d611d12..20f66e6ae19cbac1de610de59d5e73a9f7f39cec 100644
--- a/gcc/config/arm/fa606te.md
+++ b/gcc/config/arm/fa606te.md
@@ -62,8 +62,15 @@ (define_cpu_unit "fa606te_core" "fa606te
;; ALU operations
(define_insn_reservation "606te_alu_op" 1
(and (eq_attr "tune" "fa606te")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,
- extend,arlo_shift,arlo_shift_reg,\
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg,extend,\
+ alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
mov_imm,mov_reg,mov_shift,mov_shift_reg,\
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg"))
"fa606te_core")
diff --git a/gcc/config/arm/fa626te.md b/gcc/config/arm/fa626te.md
index 04d2a5cf33f25a3c54bc84dc09c192137f4bb672..c5b841c3630072c086f277628acd5c8e9d22e83d 100644
--- a/gcc/config/arm/fa626te.md
+++ b/gcc/config/arm/fa626te.md
@@ -68,13 +68,21 @@ (define_cpu_unit "fa626te_core" "fa626te
;; ALU operations
(define_insn_reservation "626te_alu_op" 1
(and (eq_attr "tune" "fa626,fa626te")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"fa626te_core")
(define_insn_reservation "626te_alu_shift_op" 2
(and (eq_attr "tune" "fa626,fa626te")
- (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
+ (eq_attr "type" "extend,\
+ alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm,\
+ alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"fa626te_core")
diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md
index 342b9bf5d33cbe2f2c74fa2ea47aa3ee936a6d53..1947d36ec09a86ae5f629271bf395bd0be59eb97 100644
--- a/gcc/config/arm/fa726te.md
+++ b/gcc/config/arm/fa726te.md
@@ -86,7 +86,11 @@ (define_insn_reservation "726te_shift_op
;; Other ALU instructions 2 cycles.
(define_insn_reservation "726te_alu_op" 1
(and (eq_attr "tune" "fa726te")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg"))
+ (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+ alu_reg,alus_reg,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg"))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
;; ALU operations with a shift-by-register operand.
@@ -95,12 +99,14 @@ (define_insn_reservation "726te_alu_op"
;; it takes 3 cycles.
(define_insn_reservation "726te_alu_shift_op" 3
(and (eq_attr "tune" "fa726te")
- (eq_attr "type" "extend,arlo_shift"))
+ (eq_attr "type" "extend,alu_shift_imm,alus_shift_imm,\
+ logic_shift_imm,logics_shift_imm"))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
(define_insn_reservation "726te_alu_shift_reg_op" 3
(and (eq_attr "tune" "fa726te")
- (eq_attr "type" "arlo_shift_reg"))
+ (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+ logic_shift_reg,logics_shift_reg"))
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Multiplication Instructions
diff --git a/gcc/config/arm/fmp626.md b/gcc/config/arm/fmp626.md
index 944645b9ead395be7950ff7dfbdcb72310cb39ff..ffb68570e3786cedd4c1cd976ee90e5b2fe714e0 100644
--- a/gcc/config/arm/fmp626.md
+++ b/gcc/config/arm/fmp626.md
@@ -63,13 +63,19 @@ (define_cpu_unit "fmp626_core" "fmp626")
;; ALU operations
(define_insn_reservation "mp626_alu_op" 1
(and (eq_attr "tune" "fmp626")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg,\
+ (eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\
+ logic_imm,logics_imm,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg,\
mov_imm,mov_reg,mvn_imm,mvn_reg"))
"fmp626_core")
(define_insn_reservation "mp626_alu_shift_op" 2
(and (eq_attr "tune" "fmp626")
- (eq_attr "type" "extend,arlo_shift,arlo_shift_reg,\
+ (eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\
+ alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\
+ extend,\
mov_shift,mov_shift_reg,\
mvn_shift,mvn_shift_reg"))
"fmp626_core")
diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md
index 3d1bf596f86cff31f3b24f3df587095e0963a400..f6e4e011c338a898ed7b0b4706966755f24bd6ac 100644
--- a/gcc/config/arm/marvell-pj4.md
+++ b/gcc/config/arm/marvell-pj4.md
@@ -53,26 +53,42 @@ (define_insn_reservation "pj4_alu_e1_con
(define_insn_reservation "pj4_alu" 1
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
+ (eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\
+ logic_imm,logics_imm,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg")
(not (eq_attr "conds" "set")))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_conds" 4
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "arlo_imm,arlo_reg,shift,shift_reg")
+ (eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\
+ logic_imm,logics_imm,logic_reg,logics_reg,\
+ adc_imm,adcs_imm,adc_reg,adcs_reg,\
+ adr,bfm,rev,\
+ shift_imm,shift_reg")
(eq_attr "conds" "set"))
"pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_shift" 1
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
+ (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
+ alus_shift_imm,logics_shift_imm,\
+ alu_shift_reg,logic_shift_reg,\
+ alus_shift_reg,logics_shift_reg,\
+ extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")
(not (eq_attr "conds" "set"))
(eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_shift_conds" 4
(and (eq_attr "tune" "marvell_pj4")
- (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
+ (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
+ alus_shift_imm,logics_shift_imm,\
+ alu_shift_reg,logic_shift_reg,\
+ alus_shift_reg,logics_shift_reg,\
+ extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg")
(eq_attr "conds" "set")
(eq_attr "shift" "1")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)")
@@ -80,14 +96,20 @@ (define_insn_reservation "pj4_shift_cond
(define_insn_reservation "pj4_alu_shift" 1
(and (eq_attr "tune" "marvell_pj4")
(not (eq_attr "conds" "set"))
- (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
+ (eq_attr "type" "alu_shift_imm,logic_shift_imm,\
+ alus_shift_imm,logics_shift_imm,\
+ alu_shift_reg,logic_shift_reg,\
+ alus_shift_reg,logics_shift_reg,\
+ extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg"))
"pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
(define_insn_reservation "pj4_alu_shift_conds" 4
(and (eq_attr "tune" "marvell_pj4")
(eq_attr "conds" "set")
- (eq_attr "type" "arlo_shift,arlo_shift_reg,extend,\
+ (eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\
+ alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\
+ extend,\
mov_shift,mvn_shift,mov_shift_reg,mvn_shift_reg"))
"pj4_is,(pj4_alu1,nothing,pj4_w1+pj4_cp)|(pj4_alu2,nothing,pj4_w2+pj4_cp)")
diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index 8b184a80c2ea3d2c0b596924364a4ca6aea0f686..895a12d8f8e8ee646bb339ecef5f992b3a2a4af7 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -36,7 +36,7 @@ (define_insn "*thumb_andsi_not_shiftsi_s
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "2")
- (set_attr "type" "arlo_shift")]
+ (set_attr "type" "alu_shift_imm")]
)
;; We use the '0' constraint for operand 1 because reload should
@@ -282,7 +282,7 @@ (define_insn "*thumb2_movsi_insn"
ldr%?\\t%0, %1
str%?\\t%1, %0
str%?\\t%1, %0"
- [(set_attr "type" "*,arlo_imm,arlo_imm,arlo_imm,*,load1,load1,store1,store1")
+ [(set_attr "type" "*,alu_imm,alu_imm,alu_imm,*,load1,load1,store1,store1")
(set_attr "length" "2,4,2,4,4,4,4,4,4")
(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no")
@@ -335,7 +335,7 @@ (define_insn "*thumb2_cmpsi_neg_shiftsi"
"cmn%?\\t%0, %1%S3"
[(set_attr "conds" "set")
(set_attr "shift" "1")
- (set_attr "type" "arlo_shift")]
+ (set_attr "type" "alus_shift_imm")]
)
(define_insn_and_split "*thumb2_mov_scc"
@@ -1087,8 +1087,8 @@ (define_insn "*thumb2_shiftsi3_short"
(set_attr "shift" "1")
(set_attr "length" "2")
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
- (const_string "arlo_shift")
- (const_string "arlo_shift_reg")))]
+ (const_string "alu_shift_imm")
+ (const_string "alu_shift_reg")))]
)
(define_insn "*thumb2_mov<mode>_shortim"
@@ -1210,7 +1210,7 @@ (define_insn "*thumb2_addsi3_compare0_sc
"
[(set_attr "conds" "set")
(set_attr "length" "2,2,4,4")
- (set_attr "type" "arlo_imm,*,arlo_imm,*")]
+ (set_attr "type" "alus_imm,alus_reg,alus_imm,alus_reg")]
)
(define_insn "*thumb2_mulsi_short"
@@ -1336,7 +1336,7 @@ (define_insn "*orsi_not_shiftsi_si"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")
(set_attr "shift" "2")
- (set_attr "type" "arlo_shift")]
+ (set_attr "type" "alu_shift_imm")]
)
(define_peephole2
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index 1b7db65f2282fd7aadb8664b27dc107d9159a9bb..14d2bee82ca37221338be7a2f59a490db0fbaf25 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -23,21 +23,37 @@
;
; Instruction classification:
;
-; arlo_imm any arithmetic or logical instruction that doesn't have
-; a shifted operand and has an immediate operand. This
+; adc_imm add/subtract with carry and with an immediate operand.
+; adc_reg add/subtract with carry and no immediate operand.
+; adcs_imm as adc_imm, setting condition flags.
+; adcs_reg as adc_reg, setting condition flags.
+; adr calculate address.
+; alu_ext From ARMv8-A: any arithmetic instruction that has a
+; sign/zero-extended.
+; AArch64 Only.
+; source operand
+; alu_imm any arithmetic instruction that doesn't have a shifted
+; operand and has an immediate operand. This
; excludes MOV, MVN and RSB(S) immediate.
-; arlo_reg any arithmetic or logical instruction that doesn't have
-; a shifted or an immediate operand. This excludes
+; alu_reg any arithmetic instruction that doesn't have a shifted
+; or an immediate operand. This excludes
; MOV and MVN but includes MOVT. This is also the default.
-; arlo_shift any arithmetic or logical instruction that has a source
-; operand shifted by a constant. This excludes
-; simple shifts.
-; arlo_shift_reg as arlo_shift, with the shift amount specified in a
+; alu_shift_imm any arithmetic instruction that has a source operand
+; shifted by a constant. This excludes simple shifts.
+; alu_shift_reg as alu_shift_imm, with the shift amount specified in a
; register.
+; alus_ext From ARMv8-A: as alu_ext, setting condition flags.
+; AArch64 Only.
+; alus_imm as alu_imm, setting condition flags.
+; alus_reg as alu_reg, setting condition flags.
+; alus_shift_imm as alu_shift_imm, setting condition flags.
+; alus_shift_reg as alu_shift_reg, setting condition flags.
+; bfm bitfield move operation.
; block blockage insn, this blocks all functional units.
; branch branch.
; call subroutine call.
; clz count leading zeros (CLZ).
+; csel From ARMv8-A: conditional select.
; extend extend instruction (SXTB, SXTH, UXTB, UXTH).
; f_cvt conversion between float and integral.
; f_flag transfer of co-processor flags to the CPSR.
@@ -54,6 +70,7 @@
; fcmp[d,s] double/single floating-point compare.
; fconst[d,s] double/single load immediate.
; fcpys single precision floating point cpy.
+; fcsel From ARMv8-A: Floating-point conditional select.
; fdiv[d,s] double/single precision floating point division.
; ffarith[d,s] double/single floating point abs/neg/cpy.
; ffma[d,s] double/single floating point fused multiply-accumulate.
@@ -66,6 +83,18 @@
; load2 load 2 words from memory to arm registers.
; load3 load 3 words from memory to arm registers.
; load4 load 4 words from memory to arm registers.
+; logic_imm any logical instruction that doesn't have a shifted
+; operand and has an immediate operand.
+; logic_reg any logical instruction that doesn't have a shifted
+; operand or an immediate operand.
+; logic_shift_imm any logical instruction that has a source operand
+; shifted by a constant. This excludes simple shifts.
+; logic_shift_reg as logic_shift_imm, with the shift amount specified in a
+; register.
+; logics_imm as logic_imm, setting condition flags.
+; logics_reg as logic_reg, setting condition flags.
+; logics_shift_imm as logic_shift_imm, setting condition flags.
+; logics_shift_reg as logic_shift_reg, setting condition flags.
; mla integer multiply accumulate.
; mlas integer multiply accumulate, flag setting.
; mov_imm simple MOV instruction that moves an immediate to
@@ -80,8 +109,10 @@
; mvn_reg inverting move instruction, register.
; mvn_shift inverting move instruction, shifted operand by a constant.
; mvn_shift_reg inverting move instruction, shifted operand by a register.
+; rbit reverse bits.
+; rev reverse bytes.
; sdiv signed division.
-; shift simple shift operation (LSL, LSR, ASR, ROR) with an
+; shift_imm simple shift operation (LSL, LSR, ASR, ROR) with an
; immediate.
; shift_reg simple shift by a register.
; smlad signed multiply accumulate dual.
@@ -250,14 +281,27 @@
; neon_vst3_vst4
(define_attr "type"
- "arlo_imm,\
- arlo_reg,\
- arlo_shift,\
- arlo_shift_reg,\
+ "adc_imm,\
+ adc_reg,\
+ adcs_imm,\
+ adcs_reg,\
+ adr,\
+ alu_ext,\
+ alu_imm,\
+ alu_reg,\
+ alu_shift_imm,\
+ alu_shift_reg,\
+ alus_ext,\
+ alus_imm,\
+ alus_reg,\
+ alus_shift_imm,\
+ alus_shift_reg,\
+ bfm,\
block,\
branch,\
call,\
clz,\
+ csel,\
extend,\
f_cvt,\
f_flag,\
@@ -282,6 +326,7 @@ (define_attr "type"
fconstd,\
fconsts,\
fcpys,\
+ fcsel,\
fdivd,\
fdivs,\
ffarithd,\
@@ -299,6 +344,14 @@ (define_attr "type"
load2,\
load3,\
load4,\
+ logic_imm,\
+ logic_reg,\
+ logic_shift_imm,\
+ logic_shift_reg,\
+ logics_imm,\
+ logics_reg,\
+ logics_shift_imm,\
+ logics_shift_reg,\
mla,\
mlas,\
mov_imm,\
@@ -311,8 +364,10 @@ (define_attr "type"
mvn_reg,\
mvn_shift,\
mvn_shift_reg,\
+ rbit,\
+ rev,\
sdiv,\
- shift,\
+ shift_imm,\
shift_reg,\
smlad,\
smladx,\
@@ -469,7 +524,7 @@ (define_attr "type"
neon_vst2_4_regs_vst3_vst4,\
neon_vst3_vst4_lane,\
neon_vst3_vst4"
- (const_string "arlo_reg"))
+ (const_string "alu_imm"))
; Is this an (integer side) multiply with a 32-bit (or smaller) result?
(define_attr "mul32" "no,yes"