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Re: [PATCH] FPU IEEE 754 for MIPS r5900


Hi JÃrgen,

Thanks for the update, looks good.

"JÃrgen Urban" <JuergenUrban@gmx.de> writes:
> Index: gcc/config.gcc
> ===================================================================
> --- gcc/config.gcc	(Revision 200583)
> +++ gcc/config.gcc	(Arbeitskopie)
> @@ -3080,7 +3080,7 @@
>    esac
>  fi
>  
> -# Infer a default setting for --with-float.
> +# Infer a default setting for --with-float and --with-fpu.
>  if test x$with_float = x; then
>    case ${target} in
>      mips64r5900-*-* | mips64r5900el-*-* | mipsr5900-*-* | mipsr5900el-*-*)
> @@ -3089,6 +3089,17 @@
>        with_float=soft
>        ;;
>    esac
> +else
> +  case ${target} in
> +    mips64r5900-*-* | mips64r5900el-*-* | mipsr5900-*-* | mipsr5900el-*-*)
> +      if test $with_float = hard; then
> +        if test x$with_fpu = x; then
> +	  # The FPU of the R5900 is 32 bit.
> +	  with_fpu=single
> +        fi
> +      fi
> +      ;;
> +  esac
>  fi

I think the --with-fpu default should be independent of the --with-float
default.  Passing -mhard-float to the default soft-float configuration
should produce the same code as configuring with --with-float=hard.

> Index: gcc/config/mips/mips.c
> ===================================================================
> --- gcc/config/mips/mips.c	(Revision 200583)
> +++ gcc/config/mips/mips.c	(Arbeitskopie)
> @@ -16830,6 +16830,19 @@
>  	target_flags &= ~MASK_FLOAT64;
>      }
>  
> +  if (TARGET_HARD_FLOAT_ABI && TARGET_FLOAT64 && TARGET_MIPS5900)
> +    {
> +      /* FPU of r5900 only supports 32 bit. */
> +      error ("unsupported combination: %s", "-march=r5900 -mfp64 -mhard-float");
> +    }
> +
> +  if (TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT && TARGET_MIPS5900)
> +    {
> +      /* FPU of r5900 only supports 32 bit. */
> +      error ("unsupported combination: %s",
> +             "-march=r5900 -mdouble-float -mhard-float");
> +    }

Only one of these should be needed, since we complain about -mfp64
-msingle-float earlier in the function.  Also, the coding conventions
say that there should be no braces for single-statement if blocks.

Here's what I installed.  Please let me know if I managed to mangle
things somehow.

Thanks,
Richard


gcc/
2013-07-26  JÃrgen Urban  <JuergenUrban@gmx.de>

	* config.gcc (mips*-*-*): Add --with-fpu support.  Make single the
	default for R5900 targets.
	* config/mips/mips.h (OPTION_DEFAULT_SPECS): Handle --with-fpu.
	(ISA_HAS_LDC1_SDC1): Set to false for TARGET_MIPS5900.
	* config/mips/mips.c (mips_option_override): Report an error for
	-march=r5900 -mhard-float -mdouble-float.  Use spu_single_format
	for -march=r5900 -mhard-float.


Index: gcc/config.gcc
===================================================================
--- gcc/config.gcc	2013-07-17 08:36:01.712940987 +0100
+++ gcc/config.gcc	2013-07-22 19:09:28.435708983 +0100
@@ -3091,6 +3091,16 @@ if test x$with_float = x; then
   esac
 fi
 
+# Infer a default setting for --with-fpu.
+if test x$with_fpu = x; then
+  case ${target} in
+    mips64r5900-*-* | mips64r5900el-*-* | mipsr5900-*-* | mipsr5900el-*-*)
+      # The R5900 FPU only supports single precision.
+      with_fpu=single
+      ;;
+  esac
+fi
+
 # Support --with-fpmath.
 if test x$with_fpmath != x; then
   case ${target} in
@@ -3469,7 +3479,7 @@ case "${target}" in
 		;;
 
 	mips*-*-*)
-		supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64 divide llsc mips-plt synci"
+		supported_defaults="abi arch arch_32 arch_64 float fpu tune tune_32 tune_64 divide llsc mips-plt synci"
 
 		case ${with_float} in
 		"" | soft | hard)
@@ -3480,6 +3490,16 @@ case "${target}" in
 			exit 1
 			;;
 		esac
+
+		case ${with_fpu} in
+		"" | single | double)
+			# OK
+			;;
+		*)
+			echo "Unknown fpu type used in --with-fpu=$with_fpu" 1>&2
+			exit 1
+			;;
+		esac
 
 		case ${with_abi} in
 		"" | 32 | o64 | n32 | 64 | eabi)
Index: gcc/config/mips/mips.h
===================================================================
--- gcc/config/mips/mips.h	2013-07-17 08:36:01.756941409 +0100
+++ gcc/config/mips/mips.h	2013-07-22 09:19:36.822510281 +0100
@@ -754,6 +754,7 @@ #define OPTION_DEFAULT_SPECS \
   {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
   {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
+  {"fpu", "%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}" }, \
   {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
   {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
   {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
@@ -859,7 +860,9 @@ #define ISA_HAS_CONDMOVE        (ISA_HAS
 				 || TARGET_LOONGSON_2EF)
 
 /* ISA has LDC1 and SDC1.  */
-#define ISA_HAS_LDC1_SDC1	(!ISA_MIPS1 && !TARGET_MIPS16)
+#define ISA_HAS_LDC1_SDC1	(!ISA_MIPS1				\
+				 && !TARGET_MIPS5900			\
+				 && !TARGET_MIPS16)
 
 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
    branch on CC, and move (both FP and non-FP) on CC.  */
Index: gcc/config/mips/mips.c
===================================================================
--- gcc/config/mips/mips.c	2013-07-17 08:54:00.233767123 +0100
+++ gcc/config/mips/mips.c	2013-07-22 19:21:49.741892184 +0100
@@ -16740,9 +16740,13 @@ mips_option_override (void)
       else
 	target_flags &= ~MASK_FLOAT64;
     }
-
   /* End of code shared with GAS.  */
 
+  /* The R5900 FPU only supports single precision.  */
+  if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT)
+    error ("unsupported combination: %s",
+	   "-march=r5900 -mhard-float -mdouble-float");
+
   /* If a -mlong* option was given, check that it matches the ABI,
      otherwise infer the -mlong* setting from the other options.  */
   if ((target_flags_explicit & MASK_LONG64) != 0)
@@ -17050,6 +17054,9 @@ mips_option_override (void)
      filling.  Registering the pass must be done at start up.  It's
      convenient to do it here.  */
   register_pass (&insert_pass_mips_machine_reorg2);
+
+  if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
+    REAL_MODE_FORMAT (SFmode) = &spu_single_format;
 }
 
 /* Swap the register information for registers I and I + 1, which


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