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Re: [PATCH] Improve folding of bitwise ops on booleans


We cannot avoid an mfcr then, either.  It would be one machine
instruction shorter though (but can be more expensive to execute,
on some CPUs).

That you get two MFCRs on 64-bit is a target bug.

Not true there.  If you look at the 64bit output you will see you are
using the one cr mfcr version in 64bit while you are grabbing the full
cr in the 32bit.  It depends on the processor but the one cr might be
better.

Yes, and it's still a bug.  Or three:

1) GCC uses the all-fields instruction instead of the one-field
form unless you use -mmfcrf (or -mcpu=power4, etc.), although
the one-field mfcr works fine on all CPUs and is never slower
(I'm not talking about mfocrf; just the plain mfcr instruction);

2) There is a define_peephole to combine two mfcr's into one
(search rs6000.md for "3 cycle delay"); for the example code,
one of the results ends up as SI and the other as DI, and
the peephole will not trigger on that;

3) That peephole should not be enabled with -mmfcrf, and of
course it should not be a peephole at all!

Without bug 2), you'd see the same behaviour on 64-bit as on
32-bit.


Segher


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