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RE: [PATCH, AArch64] Support BICS instruction in the backend
- From: "Ian Bolton" <ian dot bolton at arm dot com>
- To: "'Marcus Shawcroft'" <marcus dot shawcroft at gmail dot com>
- Cc: <gcc-patches at gcc dot gnu dot org>
- Date: Wed, 1 May 2013 18:45:22 +0100
- Subject: RE: [PATCH, AArch64] Support BICS instruction in the backend
- References: <517a802f dot 22e7420a dot 7cc3 dot 449eSMTPIN_ADDED_BROKEN at mx dot google dot com> <CAFqB+PwD5dqMMf1VbzoDwEsjaBBpCw35XzSruNFpcZnKQZZ7SA at mail dot gmail dot com>
> From: Marcus Shawcroft [mailto:marcus.shawcroft@gmail.com]
> + /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-
> 9\]+" } } */
>
> + /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+,
> x\[0-9\]+, lsl 3" } } */
>
> Ian, These two patterns have the same issue Richard just highlighted
> on your other patch, ie the first pattern will also match anything
> matched by the second pattern.
>
> /Marcus
>
I've fixed the rules in the testcases and renamed the files to match
naming conventions in the latest patch (attached).
OK to commit?
Cheers,
Ian
2013-05-01 Ian Bolton <ian.bolton@arm.com>
gcc/
* config/aarch64/aarch64.md (*and_one_cmpl<mode>3_compare0):
New pattern.
(*and_one_cmplsi3_compare0_uxtw): Likewise.
(*and_one_cmpl_<SHIFT:optab><mode>3_compare0): Likewise.
(*and_one_cmpl_<SHIFT:optab>si3_compare0_uxtw): Likewise.
testsuite/
* gcc.target/aarch64/bics_1.c: New test.
* gcc.target/aarch64/bics_2.c: Likewise.