RE: [PATCH, AArch64] Testcases for ANDS instruction

["Ian Bolton" <ian dot bolton at arm dot com>]

> From: Richard Earnshaw
> This rule
> > +  /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-
> 9\]+" } } */
> 
> Will match anything that this rule
> 
> > +  /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, w\[0-
> 9\]+, lsl 3" } } */
> 
> matches (though not vice versa).
> 
> Similarly for the x register variants.
> 

Thanks for the review. I've fixed this up in the attached patch, by
counting the number of matches for the first rule and expecting it to
match additional times to cover the overlap with the lsl based rule.

I've also renamed the testcases in line with the suggested GCC testcase
naming convention.

OK for commit?

Cheers,
Ian


2013-05-01  Ian Bolton  <ian.bolton@arm.com>

	* gcc.target/aarch64/ands_1.c: New test.
	* gcc.target/aarch64/ands_2.c: Likewise

Attachment: aarch64-ands-tests-svn-patch-v4.txt
Description: Text document