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On Tue, Apr 2, 2013 at 6:56 PM, Steven Bosscher wrote: > The SPARC back > end also calls dbr_schedule() in its machine_reorg pass to work around > errata in Atmel AT697F chips (LEON2-like, i.e. fairly new, see > r179921). Thinking about this some more: This could be fixed by inserting a machine-specific pass just after delayed-branch scheduling, like in the attached patch. I think the same is possible with the dbr_schedule call in the MIPS backend. Eric, what do you think of this approach? With those two dbr_schedule calls out of the way, it will be a lot easier to change things such that pass_free_cfg can run after pass_machine_reorg (and after pass_cleanup_barriers that can be simplified if there's still a CFG around). It will also help make the DELAY_SLOTS hack in cfgrtl.c:rest_of_pass_free_cfg redundant. I'm unsure how to test this patch. It's going through a bootstrap&test cycle on sparc64-unknown-linux-gnu at the moment (on gcc62) but there are no test cases for the errata that are being worked around... Ciao! Steven
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