[PATCH, AArch64] Make zero_extends explicit for common SImode patterns

["Ian Bolton" <ian dot bolton at arm dot com>]

Season's greetings to you! :)

I've made zero_extend versions of SI mode patterns that write
to W registers in order to make the implicit zero_extend that
they do explicit, so GCC can be smarter about when it actually
needs to plant a zero_extend (uxtw).

This patch significantly reduces the number of redundant
uxtw instructions seen in a variety of programs.

(There are further patterns that can be done, but I have them
in a separate patch that's still in development.)

OK for trunk and backport to ARM/aarch64-4.7-branch?

Cheers,
Ian


2012-12-13  Ian Bolton  <ian.bolton@arm.com>

	* gcc/config/aarch64/aarch64.md
	(*addsi3_aarch64_uxtw): New pattern.
	(*addsi3_compare0_uxtw): New pattern.
	(*add_<shift>_si_uxtw): New pattern.
	(*add_<optab><SHORT:mode>_si_uxtw): New pattern.
	(*add_<optab><SHORT:mode>_shft_si_uxtw): New pattern.
	(*add_<optab><SHORT:mode>_mult_si_uxtw): New pattern.
	(*add_<optab>si_multp2_uxtw): New pattern.
	(*addsi3_carryin_uxtw): New pattern.
	(*addsi3_carryin_alt1_uxtw): New pattern.
	(*addsi3_carryin_alt2_uxtw): New pattern.
	(*addsi3_carryin_alt3_uxtw): New pattern.
	(*add_uxtsi_multp2_uxtw): New pattern.
	(*subsi3_uxtw): New pattern.
	(*subsi3_compare0_uxtw): New pattern.
	(*sub_<shift>_si_uxtw): New pattern.
	(*sub_mul_imm_si_uxtw): New pattern.
	(*sub_<optab><SHORT:mode>_si_uxtw): New pattern.
	(*sub_<optab><SHORT:mode>_shft_si_uxtw): New pattern.
	(*sub_<optab>si_multp2_uxtw): New pattern.
	(*sub_uxtsi_multp2_uxtw): New pattern.
	(*negsi2_uxtw): New pattern.
	(*negsi2_compare0_uxtw): New pattern.
	(*neg_<shift>_si2_uxtw): New pattern.
	(*neg_mul_imm_si2_uxtw): New pattern.
	(*mulsi3_uxtw): New pattern.
	(*maddsi_uxtw): New pattern.
	(*msubsi_uxtw): New pattern.
	(*mulsi_neg_uxtw): New pattern.
	(*<su_optab>divsi3_uxtw): New pattern.

Attachment: aarch64-rzx-patch1-v2.txt
Description: Text document