[RFA/ARM] Fix PR54974: Thumb literal pools don't handle PC rounding

[Matthew Gretton-Dann <matthew dot gretton-dann at linaro dot org>]

All,

The attached patch fixes PR54974.

In Thumb when calculating the PC value for a literal load the value used is 
the current PC rounded down to the nearest multiple of 4.  The ARM backend 
currently does not take this into account when calculating literal pool 
placement.

The fix is to decrease the pool_range of all insns by 2 when generating 
Thumb code.  There is no need to change neg_pool_range values as rounding 
down here will reduce the distance of the literal pool.

The patch attached to the PR is not sufficient as we don't precisely know 
the PC when calculating literal pool ranges and so have to be conservative.

Whilst going through all the code I found the following, possibly related, 
issues that I would like some input from the ARM maintainers on (although 
they have not been touched in this patch):

1) Some Thumb-2 patterns (like thumb2_movhi_insn) have a neg_pool_range of 
250 for ldrh, where my reading of the ARMARM says the range is [-4095, 4095] 
for Thumb-2 (with appropriate rounding).  What is the reason for GCC's 
severe pessimism here?

2) thumb1_zero_extendqisi2 (and other insns) give a Thumb-1 narrow ldrb a 
pool_range of 32.  Surely the pool_range should be 0 (or *) as Thumb-1 
doesn't have a ldrb where the base-register can be PC?

Tested arm-none-linux-gnueabi cross, and with the testcase attached to the 
PR.  No added testcase in the patch as this code is sensitive to other code 
generation and so it is not easy to generate a testcase which will reliably 
test this condition.

OK for trunk, 4.7, and 4.6?

Thanks,

Matt

gcc/ChangeLog:

2012-11-21  Matthew Gretton-Dann  <matthew.gretton-dann@linaro.org>

	PR target/54974
	* config/arm/arm.md (thumb1_extendhisi2): Reduce Thumb
	pool_range.
	(arm_movdi): Likewise.
	(thumb1_movdi_insn): Likewise.
	(thumb1_movsi_insn): Likewise.
	(pic_load_addr_unified): Likewise.
	(pic_load_addr_32bit): Likewise.
	(pic_load_addr_thumb1): Likewise.
	(thumb1_movhf): Likewise.
	(arm_movsf_soft_insn): Likewise.
	(thumb1_movsf_soft_insn): Likewise.
	(movdf_soft_insn): Likewise.
	(thumb1_movdf_soft_insn): Likewise.
	* config/arm/neon.md (*neon_mov<mode>): Likewise.
	(*neon_mov<mode>): Likwise.
	* config/arm/thumb2.md: (*thumb2_movsi_insn): Likewise.
	(*thumb2_movhi_insn): Likewise.
	(*thumb2_extendqisi_v6): Likewise.
	(*thumb2_zero_extendqisi_v6): Likewise.
	(*thumb2_zero_extendqisi2_v6): Likewise.
	* config/arm/vfp.md: (*thumb2_movsi_vfp): Likewise.
	(*movdi_vfp): Likewise.
	(*movdi_vfp_cortexa8): Likewise.
	(*thumb2_movsf_vfp): Likewise.
	(*thumb2_movdf_vfp): Likewise.

--
Matthew Gretton-Dann
Linaro Toolchain Working Group
matthew.gretton-dann@linaro.org

Attachment: thumb-literal-pools.txt
Description: Text document