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[Patch,avr]: Fix PR54815
- From: Georg-Johann Lay <avr at gjlay dot de>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Denis Chertykov <chertykov at gmail dot com>, Eric Weddington <eric dot weddington at atmel dot com>
- Date: Fri, 05 Oct 2012 16:29:33 +0200
- Subject: [Patch,avr]: Fix PR54815
avr-gcc compiles code like
void f (int, int);
void f_or (int x)
{
f (x, x | 42);
}
to
f_or:
ldi r22,lo8(42) ; 15 *movhi/5 [length = 2]
ldi r23,0
or r22,r24 ; 6 iorhi3/1 [length = 2]
or r23,r25
rjmp f
but this is more efficient:
f_or:
movw r22,r24 ; 15 *movhi/1 [length = 1]
ori r22,42 ; 6 iorhi3/3 [length = 1]
rjmp f ; 9 call_insn/4 [length = 1]
The second variant is generated with the attached patch which makes
alternatives where the 3rd operand is a register slightly more expensive.
The saturated additions and subtractions in avr-fixed.md already contain such
constraint costs, so they need not to be fixed.
Ok for trunk?
Johann
PR target/54815
* config/avr/avr.md (*add<mode>3, add<mode>3, addpsi3): Make
constraint alternative "r,0,r" slighly more expensive.
(sub<mode>3,
(andqi3, andhi3, andpsi3, andsi3): Ditto.
(iorqi3, iorhi3, iorpsi3, iorsi3): Ditto.
(xorhi3, xorpsi3, xorsi3): Ditto.
Index: config/avr/avr.md
===================================================================
--- config/avr/avr.md (revision 192090)
+++ config/avr/avr.md (working copy)
@@ -1177,7 +1177,7 @@ (define_insn "*addhi3_sp"
;; "*addhq3" "*adduhq3"
;; "*addha3" "*adduha3"
(define_insn "*add<mode>3"
- [(set (match_operand:ALL2 0 "register_operand" "=?r,d,!w ,d")
+ [(set (match_operand:ALL2 0 "register_operand" "=??r,d,!w ,d")
(plus:ALL2 (match_operand:ALL2 1 "register_operand" "%0,0,0 ,0")
(match_operand:ALL2 2 "nonmemory_or_const_operand" "r,s,IJ YIJ,n Ynn")))]
""
@@ -1244,7 +1244,7 @@ (define_insn "add<mode>3_clobber"
;; "addsq3" "addusq3"
;; "addsa3" "addusa3"
(define_insn "add<mode>3"
- [(set (match_operand:ALL4 0 "register_operand" "=r,d ,r")
+ [(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
(plus:ALL4 (match_operand:ALL4 1 "register_operand" "%0,0 ,0")
(match_operand:ALL4 2 "nonmemory_operand" "r,i ,n Ynn")))
(clobber (match_scratch:QI 3 "=X,X ,&d"))]
@@ -1302,7 +1302,7 @@ (define_insn "*addsi3_zero_extend.hi"
(set_attr "cc" "set_n")])
(define_insn "addpsi3"
- [(set (match_operand:PSI 0 "register_operand" "=r,d ,d,r")
+ [(set (match_operand:PSI 0 "register_operand" "=??r,d ,d,r")
(plus:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0,0")
(match_operand:PSI 2 "nonmemory_operand" "r,s ,n,n")))
(clobber (match_scratch:QI 3 "=X,X ,X,&d"))]
@@ -1356,7 +1356,7 @@ (define_insn "*subpsi3_sign_extend.hi"
;; "subqi3"
;; "subqq3" "subuqq3"
(define_insn "sub<mode>3"
- [(set (match_operand:ALL1 0 "register_operand" "=r,d ,r ,r ,r ,r")
+ [(set (match_operand:ALL1 0 "register_operand" "=??r,d ,r ,r ,r ,r")
(minus:ALL1 (match_operand:ALL1 1 "register_operand" "0,0 ,0 ,0 ,0 ,0")
(match_operand:ALL1 2 "nonmemory_or_const_operand" "r,n Ynn,Y01,Ym1,Y02,Ym2")))]
""
@@ -1374,7 +1374,7 @@ (define_insn "sub<mode>3"
;; "subhq3" "subuhq3"
;; "subha3" "subuha3"
(define_insn "sub<mode>3"
- [(set (match_operand:ALL2 0 "register_operand" "=r,d ,*r")
+ [(set (match_operand:ALL2 0 "register_operand" "=??r,d ,*r")
(minus:ALL2 (match_operand:ALL2 1 "register_operand" "0,0 ,0")
(match_operand:ALL2 2 "nonmemory_or_const_operand" "r,i Ynn,Ynn")))
(clobber (match_scratch:QI 3 "=X,X ,&d"))]
@@ -1411,7 +1411,7 @@ (define_insn "*subhi3.sign_extend2"
;; "subsq3" "subusq3"
;; "subsa3" "subusa3"
(define_insn "sub<mode>3"
- [(set (match_operand:ALL4 0 "register_operand" "=r,d ,r")
+ [(set (match_operand:ALL4 0 "register_operand" "=??r,d ,r")
(minus:ALL4 (match_operand:ALL4 1 "register_operand" "0,0 ,0")
(match_operand:ALL4 2 "nonmemory_or_const_operand" "r,n Ynn,Ynn")))
(clobber (match_scratch:QI 3 "=X,X ,&d"))]
@@ -2932,7 +2932,7 @@ (define_insn "*udivmodsi4_call"
; and
(define_insn "andqi3"
- [(set (match_operand:QI 0 "register_operand" "=r,d")
+ [(set (match_operand:QI 0 "register_operand" "=??r,d")
(and:QI (match_operand:QI 1 "register_operand" "%0,0")
(match_operand:QI 2 "nonmemory_operand" "r,i")))]
""
@@ -2943,7 +2943,7 @@ (define_insn "andqi3"
(set_attr "cc" "set_zn,set_zn")])
(define_insn "andhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,d,d,r ,r")
+ [(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r")
(and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0")
(match_operand:HI 2 "nonmemory_operand" "r,s,n,Ca2,n")))
(clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))]
@@ -2961,7 +2961,7 @@ (define_insn "andhi3"
(set_attr "cc" "set_n,set_n,clobber,clobber,clobber")])
(define_insn "andpsi3"
- [(set (match_operand:PSI 0 "register_operand" "=r,d,r ,r")
+ [(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r")
(and:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,0")
(match_operand:PSI 2 "nonmemory_operand" "r,n,Ca3,n")))
(clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
@@ -2979,7 +2979,7 @@ (define_insn "andpsi3"
(set_attr "cc" "set_n,clobber,clobber,clobber")])
(define_insn "andsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,d,r ,r")
+ [(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r")
(and:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0")
(match_operand:SI 2 "nonmemory_operand" "r,n,Ca4,n")))
(clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
@@ -3014,7 +3014,7 @@ (define_peephole2 ; andi
;; ior
(define_insn "iorqi3"
- [(set (match_operand:QI 0 "register_operand" "=r,d")
+ [(set (match_operand:QI 0 "register_operand" "=??r,d")
(ior:QI (match_operand:QI 1 "register_operand" "%0,0")
(match_operand:QI 2 "nonmemory_operand" "r,i")))]
""
@@ -3025,7 +3025,7 @@ (define_insn "iorqi3"
(set_attr "cc" "set_zn,set_zn")])
(define_insn "iorhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,d,d,r ,r")
+ [(set (match_operand:HI 0 "register_operand" "=??r,d,d,r ,r")
(ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0 ,0")
(match_operand:HI 2 "nonmemory_operand" "r,s,n,Co2,n")))
(clobber (match_scratch:QI 3 "=X,X,X,X ,&d"))]
@@ -3043,7 +3043,7 @@ (define_insn "iorhi3"
(set_attr "cc" "set_n,set_n,clobber,clobber,clobber")])
(define_insn "iorpsi3"
- [(set (match_operand:PSI 0 "register_operand" "=r,d,r ,r")
+ [(set (match_operand:PSI 0 "register_operand" "=??r,d,r ,r")
(ior:PSI (match_operand:PSI 1 "register_operand" "%0,0,0 ,0")
(match_operand:PSI 2 "nonmemory_operand" "r,n,Co3,n")))
(clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
@@ -3061,7 +3061,7 @@ (define_insn "iorpsi3"
(set_attr "cc" "set_n,clobber,clobber,clobber")])
(define_insn "iorsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,d,r ,r")
+ [(set (match_operand:SI 0 "register_operand" "=??r,d,r ,r")
(ior:SI (match_operand:SI 1 "register_operand" "%0,0,0 ,0")
(match_operand:SI 2 "nonmemory_operand" "r,n,Co4,n")))
(clobber (match_scratch:QI 3 "=X,X,X ,&d"))]
@@ -3092,7 +3092,7 @@ (define_insn "xorqi3"
(set_attr "cc" "set_zn")])
(define_insn "xorhi3"
- [(set (match_operand:HI 0 "register_operand" "=r,r ,r")
+ [(set (match_operand:HI 0 "register_operand" "=??r,r ,r")
(xor:HI (match_operand:HI 1 "register_operand" "%0,0 ,0")
(match_operand:HI 2 "nonmemory_operand" "r,Cx2,n")))
(clobber (match_scratch:QI 3 "=X,X ,&d"))]
@@ -3108,7 +3108,7 @@ (define_insn "xorhi3"
(set_attr "cc" "set_n,clobber,clobber")])
(define_insn "xorpsi3"
- [(set (match_operand:PSI 0 "register_operand" "=r,r ,r")
+ [(set (match_operand:PSI 0 "register_operand" "=??r,r ,r")
(xor:PSI (match_operand:PSI 1 "register_operand" "%0,0 ,0")
(match_operand:PSI 2 "nonmemory_operand" "r,Cx3,n")))
(clobber (match_scratch:QI 3 "=X,X ,&d"))]
@@ -3126,7 +3126,7 @@ (define_insn "xorpsi3"
(set_attr "cc" "set_n,clobber,clobber")])
(define_insn "xorsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,r ,r")
+ [(set (match_operand:SI 0 "register_operand" "=??r,r ,r")
(xor:SI (match_operand:SI 1 "register_operand" "%0,0 ,0")
(match_operand:SI 2 "nonmemory_operand" "r,Cx4,n")))
(clobber (match_scratch:QI 3 "=X,X ,&d"))]