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[Patch][AArch64] Tighten predicate for CMP pattern.
- From: Tejas Belagod <tbelagod at arm dot com>
- To: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 10 Sep 2012 16:11:31 +0100
- Subject: [Patch][AArch64] Tighten predicate for CMP pattern.
Hi,
This patch tightens the predicate for the CMP pattern. It makes it restrictive
to accept reg or zero as prescribed by the architecture.
Regression-tested on aarch64-none-elf. OK for aarch64-branch?
Thanks,
Tejas Belagod
ARM.
PS: This patch applies over vldn-vstn.txt sent out earlier.
Changelog:
2012-09-10 Tejas Belagod <tejas.belagod@arm.com>
gcc/
* config/aarch64/aarch64-simd.md (aarch64_cm<cmp><mode>): Tighten
predicate for operand 2 of the compare pattern to accept register
or zero.
* config/aarch64/predicates.md (aarch64_simd_reg_or_zero): New.
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index d3f8ef2..50114aa 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -2670,7 +2670,7 @@
[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")
(unspec:<V_cmp_result>
[(match_operand:VSDQ_I_DI 1 "register_operand" "w,w")
- (match_operand:VSDQ_I_DI 2 "nonmemory_operand" "w,Z")]
+ (match_operand:VSDQ_I_DI 2 "aarch64_simd_reg_or_zero" "w,Z")]
VCMP_S))]
"TARGET_SIMD"
"@
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 328e5cf..f40ab56 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -265,3 +265,10 @@
{
return aarch64_simd_shift_imm_p (op, mode, false);
})
+
+(define_predicate "aarch64_simd_reg_or_zero"
+ (and (match_code "reg,subreg,const_int,const_vector")
+ (ior (match_operand 0 "register_operand")
+ (ior (match_test "op == const0_rtx")
+ (match_test "aarch64_simd_imm_zero_p (op, mode)")))))
+