This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
[AArch64] cache CTR_EL0 in sync_cache_range()
- From: Marcus Shawcroft <marcus dot shawcroft at arm dot com>
- To: "gcc >> \"gcc-patches at gcc dot gnu dot org\"" <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 03 Sep 2012 10:55:54 +0100
- Subject: [AArch64] cache CTR_EL0 in sync_cache_range()
I've just committed the attached patch to cache the CTR_EL0 register
between calls to sync_cache_range().
/Marcus
2012-09-03 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/sync-cache.c (__aarch64_sync_cache_range):
Cache the ctr_el0 register.
diff --git a/libgcc/config/aarch64/sync-cache.c b/libgcc/config/aarch64/sync-cache.c
index 1636b94..d7b621e 100644
--- a/libgcc/config/aarch64/sync-cache.c
+++ b/libgcc/config/aarch64/sync-cache.c
@@ -21,14 +21,15 @@
void
__aarch64_sync_cache_range (const void *base, const void *end)
{
- unsigned int cache_info = 0;
- unsigned int icache_lsize;
- unsigned int dcache_lsize;
+ unsigned icache_lsize;
+ unsigned dcache_lsize;
+ static unsigned int cache_info = 0;
const char *address;
- /* CTR_EL0 [3:0] contains log2 of icache line size in words.
- CTR_EL0 [19:16] contains log2 of dcache line size in words. */
- asm volatile ("mrs\t%0, ctr_el0":"=r" (cache_info));
+ if (! cache_info)
+ /* CTR_EL0 [3:0] contains log2 of icache line size in words.
+ CTR_EL0 [19:16] contains log2 of dcache line size in words. */
+ asm volatile ("mrs\t%0, ctr_el0":"=r" (cache_info));
icache_lsize = 4 << (cache_info & 0xF);
dcache_lsize = 4 << ((cache_info >> 16) & 0xF);