[PATCH v3, i386]: Fix PR46829 and PR46843, ICE in spill_failure with -fschedule-insns on x86

[Uros Bizjak <ubizjak at gmail dot com>]

Hello!

Attached patch implements TARGET_COMBINE_REJECT_INSN target hook [1] for x86.

The patched gcc rejects combined instructions with hard registers that
don't fit operand constraints, and this way helps reload to avoid
spill failures. Please note that critical instructions include
instructions like integer division, multiplication, variable shifts
and various string instructions that already require eax, edx and/or
ecx registers at exactly the right spot. Having this valuable register
at the wrong place could trigger the spill failure, since reload is
unable to solve the mess.

The situation is even more critical with insn scheduling, since
various moves to and from critical registers get scheduled before or
after critical instruction, increasing register pressure. A follow-up
patch from Yuri will enable priority scheduling for hard reg moves and
this will hopefully allow us to enable scheduling for various x86
targets.

2012-08-23  Uros Bizjak  <ubizjak@gmail.com>

	PR target/46829
	PR target/46843
	* config/i386/i386.c (ix86_reject_combined_insn): New function.
	(TARGET_REJECT_COMBINED_INSN): New macro.

testsuite/ChangeLog:

2012-08-23  Uros Bizjak  <ubizjak@gmail.com>

	PR target/46829
	PR target/46843
	* gcc.target/i386/pr46829.c: New test.
	* gcc.target/i386/pr46843.c: New test.

Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu {,-m32}.

I will wait a couple of days with the patch, so eventual effects on
benchmarks can be analysed.

[1] http://gcc.gnu.org/ml/gcc-patches/2012-08/msg01594.html

Uros.

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