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[SH] Minor prefetch insn corrections


Hello,

I've noticed that __builtin_prefetch was not working on SH3, although
the pref instruction is available on SH3.  Also, it seems that some of
the checks in the prefetch expander are redundant.
Tested on rev 190273 with
make -k check RUNTESTFLAGS="--target_board=sh-sim
\{-m2/-ml,-m2/-mb,-m2a/-mb,-m4/-ml,-m4/-mb,-m4a/-ml,-m4a/-mb}"

and no new failures.
OK?

Cheers,
Oleg

ChangeLog:

	* config/sh/sh.md (prefetch): Simplify expander.  Fix condition
	to allow SH3.
	(*prefetch_media): Move insn below expander.
	(*prefetch): Fix condition to allow SH3.

testsuite/ChangeLog:

	* gcc.target/sh/prefetch.c: Add -m3* to inclusion list.
Index: gcc/config/sh/sh.md
===================================================================
--- gcc/config/sh/sh.md	(revision 190259)
+++ gcc/config/sh/sh.md	(working copy)
@@ -13731,44 +13731,36 @@
   "byterev	%1, %0"
   [(set_attr "type" "arith_media")])
 
-(define_insn "*prefetch_media"
-  [(prefetch (match_operand:QI 0 "address_operand" "p")
-             (match_operand:SI 1 "const_int_operand" "n")
-             (match_operand:SI 2 "const_int_operand" "n"))]
-  "TARGET_SHMEDIA"
-{
-  operands[0] = gen_rtx_MEM (QImode, operands[0]);
-  output_asm_insn ("ld%M0.b    %m0,r63", operands);
-  return "";
-}
-  [(set_attr "type" "other")])
-
 ;; In user mode, the "pref" instruction will raise a RADDERR exception
 ;; for accesses to [0x80000000,0xffffffff].  This makes it an unsuitable
 ;; implementation of __builtin_prefetch for VxWorks RTPs.
 (define_expand "prefetch"
-  [(prefetch (match_operand 0 "address_operand" "p")
-             (match_operand:SI 1 "const_int_operand" "n")
-             (match_operand:SI 2 "const_int_operand" "n"))]
-  "TARGET_SH2A || ((TARGET_HARD_SH4 || TARGET_SH5)
-   && (TARGET_SHMEDIA || !TARGET_VXWORKS_RTP))"
-{
-  if (GET_MODE (operands[0]) != Pmode
-      || !CONST_INT_P (operands[1])
-      || !CONST_INT_P (operands[2]))
-    FAIL;
-  if (! TARGET_SHMEDIA)
-    operands[0] = force_reg (Pmode, operands[0]);
-})
+  [(prefetch (match_operand 0 "address_operand" "")
+             (match_operand:SI 1 "const_int_operand" "")
+             (match_operand:SI 2 "const_int_operand" ""))]
+  "(TARGET_SH2A || TARGET_SH3 || TARGET_SH5)
+   && (TARGET_SHMEDIA || ! TARGET_VXWORKS_RTP)")
 
 (define_insn "*prefetch"
   [(prefetch (match_operand:SI 0 "register_operand" "r")
 	     (match_operand:SI 1 "const_int_operand" "n")
 	     (match_operand:SI 2 "const_int_operand" "n"))]
-  "(TARGET_SH2A || TARGET_HARD_SH4 || TARGET_SHCOMPACT) && !TARGET_VXWORKS_RTP"
+  "(TARGET_SH2A || TARGET_SH3 || TARGET_SHCOMPACT) && ! TARGET_VXWORKS_RTP"
   "pref	@%0"
   [(set_attr "type" "other")])
 
+(define_insn "*prefetch_media"
+  [(prefetch (match_operand:QI 0 "address_operand" "p")
+             (match_operand:SI 1 "const_int_operand" "n")
+             (match_operand:SI 2 "const_int_operand" "n"))]
+  "TARGET_SHMEDIA"
+{
+  operands[0] = gen_rtx_MEM (QImode, operands[0]);
+  output_asm_insn ("ld%M0.b    %m0,r63", operands);
+  return "";
+}
+  [(set_attr "type" "other")])
+
 (define_insn "alloco_i"
   [(set (mem:BLK (match_operand:QI 0 "cache_address_operand" "p"))
 	(unspec:BLK [(const_int 0)] UNSPEC_ALLOCO))]
Index: gcc/testsuite/gcc.target/sh/prefetch.c
===================================================================
--- gcc/testsuite/gcc.target/sh/prefetch.c	(revision 190256)
+++ gcc/testsuite/gcc.target/sh/prefetch.c	(working copy)
@@ -2,7 +2,7 @@
    instruction PREF @Rm.  */
 /* { dg-do assemble {target sh*-*-*}}  */
 /* { dg-options "-O0" }  */
-/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" "-m4*" } }  */
+/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" "-m3*" "-m4*" } }  */
 /* { dg-final { scan-assembler "pref"} }  */
 
 void

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