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RE: [PATCH, gcc/doc]: Document AMD btver2 enablement
- From: "Kumar, Venkataramanan" <Venkataramanan dot Kumar at amd dot com>
- To: Gerald Pfeifer <gerald at pfeifer dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Sun, 5 Aug 2012 12:33:12 +0000
- Subject: RE: [PATCH, gcc/doc]: Document AMD btver2 enablement
- References: <20120804173745.4816.23890.sendpatchset@adcelk01.amd.com> <alpine.LNX.2.00.1208042049430.3055@gerinyyl.fvgr>
Hi Gerald,
Thank you. I committed changes as per your review comments.
Ref: http://gcc.gnu.org/viewcvs?view=revision&revision=190151
Regards,
Venkat.
> -----Original Message-----
> From: Gerald Pfeifer [mailto:gerald@pfeifer.com]
> Sent: Sunday, August 05, 2012 12:24 AM
> To: Kumar, Venkataramanan
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH, gcc/doc]: Document AMD btver2 enablement
>
> On Sat, 4 Aug 2012, venkataramanan.kumar@amd.com wrote:
> > Index: gcc/doc/extend.texi
> > ===================================================================
> > +@item btver1
> > +AMD family 14h cpu.
>
> CPU...
>
> > @item amdfam15h
> > AMD family 15h CPU.
>
> ...like you already had here. :-)
>
> > +@item btver2
> > +AMD family 16h cpu.
>
> CPU.
>
> > +@item btver2
> > +CPUs based on AMD Family 16h cores with x86-64 instruction set support.
> (This
> > +supersets MOVBE, F16C, BMI, AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM,
> > +SSE4A, SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction set extensions.)
>
> I could not find "supsersets" as a verb in my dictionary: how
> about "includes"?
>
> And I'd omit the parentheses around the second sentence, but this is
> just a preference on my side; feel free to keep them if you prefer.
>
> Okay with these changes.
>
> Thanks,
> Gerald