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[PATCH, MIPS] 74k madd scheduler tweaks


The existing scheduler bypass information for madd on the 74k uses some bits copied from the 24k, and is not quite correct. This patch is based on one originally sent to us by MIPS and has been present in our local source base for years. I've confirmed that we are legally allowed to contribute this to the FSF; ok for mainline?

-Sandra

2012-08-01  Sandra Loosemore  <sandra@codesourcery.com>
	    Maxim Kuvyrkov  <maxim@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>
	    MIPS Technologies, Inc.
	
	* config/mips/74k.md (r74k_int_mult, r74k_int_madd): Don't use
	mips_linked_madd_p for bypasses.
	(r74k_int_mul3): Use mips_mult_madd_chain_bypass_p for bypass.
	* config/mips/mips.c (mips_mult_madd_chain_bypass_p): New.
	* config/mips/mips-protos.h (mips_mult_madd_chain_bypass_p): Add
	prototype.


Index: gcc/config/mips/74k.md
===================================================================
--- gcc/config/mips/74k.md	(revision 189988)
+++ gcc/config/mips/74k.md	(working copy)
@@ -168,10 +168,11 @@
 ;; mult/madd/msub->int_mfhilo  : 4 cycles (default)
 ;; mult->madd/msub             : 1 cycles
 ;; madd/msub->madd/msub        : 1 cycles
-(define_bypass 1 "r74k_int_mult,r74k_int_mul3" "r74k_int_madd"
-  "mips_linked_madd_p")
-(define_bypass 1 "r74k_int_madd" "r74k_int_madd"
-  "mips_linked_madd_p")
+(define_bypass 1 "r74k_int_mult" "r74k_int_madd")
+(define_bypass 1 "r74k_int_madd" "r74k_int_madd")
+
+(define_bypass 1 "r74k_int_mul3" "r74k_int_madd"
+  "mips_mult_madd_chain_bypass_p")
 
 ;; --------------------------------------------------------------
 ;; Floating Point Instructions
Index: gcc/config/mips/mips-protos.h
===================================================================
--- gcc/config/mips/mips-protos.h	(revision 189988)
+++ gcc/config/mips/mips-protos.h	(working copy)
@@ -296,6 +296,7 @@ extern unsigned int mips_sync_loop_insns
 extern const char *mips_output_division (const char *, rtx *);
 extern unsigned int mips_hard_regno_nregs (int, enum machine_mode);
 extern bool mips_linked_madd_p (rtx, rtx);
+extern bool mips_mult_madd_chain_bypass_p (rtx, rtx);
 extern bool mips_store_data_bypass_p (rtx, rtx);
 extern rtx mips_prefetch_cookie (rtx, rtx);
 
Index: gcc/config/mips/mips.c
===================================================================
--- gcc/config/mips/mips.c	(revision 189988)
+++ gcc/config/mips/mips.c	(working copy)
@@ -12392,6 +12392,18 @@ mips_linked_madd_p (rtx out_insn, rtx in
   return false;
 }
 
+/* Helper function for 74k; returns true to enable the chained mult/madd
+   bypass.  */
+bool
+mips_mult_madd_chain_bypass_p (rtx out_insn ATTRIBUTE_UNUSED,
+			       rtx in_insn ATTRIBUTE_UNUSED)
+{
+  if (reload_completed)
+    return false;
+  else
+    return true;
+}
+
 /* True if the dependency between OUT_INSN and IN_INSN is on the store
    data rather than the address.  We need this because the cprestore
    pattern is type "store", but is defined using an UNSPEC_VOLATILE,

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