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RE: [4.6][ARM] Backport "MCR Not available in Thumb1"
- From: "Joey Ye" <joey dot ye at arm dot com>
- To: "Richard Earnshaw" <Richard dot Earnshaw at arm dot com>
- Cc: "GCC Patches" <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 19 Jun 2012 19:26:50 +0800
- Subject: RE: [4.6][ARM] Backport "MCR Not available in Thumb1"
- References: <000001cd4dc8$2734ebb0$759ec310$@ye@arm.com> <4FE03B77.7030500@arm.com>
Oops! Sorry for such a stupid problem.
2012-06-18 Joey Ye <joey.ye@arm.com>
Backported from mainline
2011-10-14 David Alan Gilbert <david.gilbert@linaro.org>
* config/arm/arm.h (TARGET_HAVE_DMB_MCR): MCR Not available in
Thumb1.
Index: gcc/config/arm/arm.h
===================================================================
--- gcc/config/arm/arm.h (revision 188331)
+++ gcc/config/arm/arm.h (working copy)
@@ -294,7 +294,8 @@
#define TARGET_HAVE_DMB (arm_arch7)
/* Nonzero if this chip implements a memory barrier via CP15. */
-#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
+#define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \
+ && ! TARGET_THUMB1)
/* Nonzero if this chip implements a memory barrier instruction. */
#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
> -----Original Message-----
> From: Richard Earnshaw
> Sent: Tuesday, June 19, 2012 16:43
> To: Joey Ye
> Cc: GCC Patches
> Subject: Re: [4.6][ARM] Backport "MCR Not available in Thumb1"
>
> On 19/06/12 04:03, Joey Ye wrote:
> > Backporting trunk r179979
> >
> > OK for 4.6?
> >
> > Backported from mainline
> > 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org>
> >
> > PR target/48126
> > * config/arm/arm.c (arm_output_sync_loop): Move label before
> > barrier.
> >
> > Index: gcc/config/arm/arm.h
> > ===================================================================
> > --- gcc/config/arm/arm.h (revision 188331)
> > +++ gcc/config/arm/arm.h (working copy)
> > @@ -294,7 +294,8 @@
> > #define TARGET_HAVE_DMB (arm_arch7)
> >
> > /* Nonzero if this chip implements a memory barrier via CP15. */
> > -#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
> > +#define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \
> > + && ! TARGET_THUMB1)
> >
> > /* Nonzero if this chip implements a memory barrier instruction. */
> > #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB ||
> TARGET_HAVE_DMB_MCR)
> >
> >
>
> Not ok (yet), the ChangeLog entry doesn't match the patch.
>
> R.