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Re: [4.6][ARM] Backport fix PR48126
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: Joey Ye <joey dot ye at arm dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 18 Jun 2012 15:49:05 +0100
- Subject: Re: [4.6][ARM] Backport fix PR48126
- References: <000a01cd4d00$006b6770$01423650$@ye@arm.com>
On 18/06/12 04:11, Joey Ye wrote:
> OK for 4.6?
>
> 2012-06-18 Joey Ye <joey.ye@arm.com>
>
> Backport from mainline
> 2011-10-14 David Alan Gilbert <david.gilbert@linaro.org>
>
> PR target/48126
> * config/arm/arm.c (arm_output_sync_loop): Move label before
> barrier.
>
>
> Index: gcc/config/arm/arm.c
> ===================================================================
> --- gcc/config/arm/arm.c (revision 188331)
> +++ gcc/config/arm/arm.c (working copy)
> @@ -23423,8 +23423,11 @@
> }
> }
>
> + /* Note: label is before barrier so that in cmp failure case we still get
> + a barrier to stop subsequent loads floating upwards past the ldrex
> + PR target/48126. */
> + arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:",
> LOCAL_LABEL_PREFIX);
> arm_process_output_memory_barrier (emit, NULL);
> - arm_output_asm_insn (emit, 1, operands, "%sLSYB%%=:",
> LOCAL_LABEL_PREFIX);
> }
>
This bit is OK...
> static rtx
> Index: gcc/config/arm/arm.h
> ===================================================================
> --- gcc/config/arm/arm.h (revision 188331)
> +++ gcc/config/arm/arm.h (working copy)
> @@ -294,7 +294,8 @@
> #define TARGET_HAVE_DMB (arm_arch7)
>
> /* Nonzero if this chip implements a memory barrier via CP15. */
> -#define TARGET_HAVE_DMB_MCR (arm_arch6k && ! TARGET_HAVE_DMB)
> +#define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \
> + && ! TARGET_THUMB1)
>
> /* Nonzero if this chip implements a memory barrier instruction. */
> #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
>
... but this bit has nothing to do with what you've described.
R.