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[PATCH] arm: Fix iwmmxt shift and logical intrinsics (PR 35294).
- From: Matt Turner <mattst88 at gmail dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Nick Clifton <nickc at redhat dot com>, Richard Earnshaw <richard dot earnshaw at arm dot com>, Paul Brook <paul at codesourcery dot com>, Ramana Radhakrishnan <ramana dot radhakrishnan at arm dot com>, Matt Turner <mattst88 at gmail dot com>
- Date: Fri, 24 Feb 2012 22:53:34 -0500
- Subject: [PATCH] arm: Fix iwmmxt shift and logical intrinsics (PR 35294).
- Authentication-results: mr.google.com; spf=pass (google.com: domain of mattst88@gmail.com designates 10.236.184.129 as permitted sender) smtp.mail=mattst88@gmail.com; dkim=pass header.i=mattst88@gmail.com
PR 36798 and 36966 are duplicates.
2012-02-24 Matt Turner <mattst88@gmail.com>
PR target/35294
* config/arm/arm.c (arm_expand_builtin): Wire up missing
intrinsics.
---
gcc/config/arm/arm.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 61 insertions(+), 1 deletions(-)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 7f0dc6b..f5935d6 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -20502,7 +20502,8 @@ arm_expand_binop_builtin (enum insn_code icode,
|| ! (*insn_data[icode].operand[0].predicate) (target, tmode))
target = gen_reg_rtx (tmode);
- gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
+ gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode)
+ && (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode));
if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
op0 = copy_to_mode_reg (mode0, op0);
@@ -21181,6 +21182,65 @@ arm_expand_builtin (tree exp,
emit_insn (pat);
return target;
+ case ARM_BUILTIN_WSLLH:
+ case ARM_BUILTIN_WSLLHI:
+ case ARM_BUILTIN_WSLLW:
+ case ARM_BUILTIN_WSLLWI:
+ case ARM_BUILTIN_WSLLD:
+ case ARM_BUILTIN_WSLLDI:
+ case ARM_BUILTIN_WSRAH:
+ case ARM_BUILTIN_WSRAHI:
+ case ARM_BUILTIN_WSRAW:
+ case ARM_BUILTIN_WSRAWI:
+ case ARM_BUILTIN_WSRAD:
+ case ARM_BUILTIN_WSRADI:
+ case ARM_BUILTIN_WSRLH:
+ case ARM_BUILTIN_WSRLHI:
+ case ARM_BUILTIN_WSRLW:
+ case ARM_BUILTIN_WSRLWI:
+ case ARM_BUILTIN_WSRLD:
+ case ARM_BUILTIN_WSRLDI:
+ case ARM_BUILTIN_WRORH:
+ case ARM_BUILTIN_WRORHI:
+ case ARM_BUILTIN_WRORW:
+ case ARM_BUILTIN_WRORWI:
+ case ARM_BUILTIN_WRORD:
+ case ARM_BUILTIN_WRORDI:
+ case ARM_BUILTIN_WAND:
+ case ARM_BUILTIN_WANDN:
+ case ARM_BUILTIN_WOR:
+ case ARM_BUILTIN_WXOR:
+ icode = (fcode == ARM_BUILTIN_WSLLH ? CODE_FOR_ashlv4hi3_di
+ : fcode == ARM_BUILTIN_WSLLHI ? CODE_FOR_ashlv4hi3_iwmmxt
+ : fcode == ARM_BUILTIN_WSLLW ? CODE_FOR_ashlv2si3_di
+ : fcode == ARM_BUILTIN_WSLLWI ? CODE_FOR_ashlv2si3_iwmmxt
+ : fcode == ARM_BUILTIN_WSLLD ? CODE_FOR_ashldi3_di
+ : fcode == ARM_BUILTIN_WSLLDI ? CODE_FOR_ashldi3_iwmmxt
+ : fcode == ARM_BUILTIN_WSRAH ? CODE_FOR_ashrv4hi3_di
+ : fcode == ARM_BUILTIN_WSRAHI ? CODE_FOR_ashrv4hi3_iwmmxt
+ : fcode == ARM_BUILTIN_WSRAW ? CODE_FOR_ashrv2si3_di
+ : fcode == ARM_BUILTIN_WSRAWI ? CODE_FOR_ashrv2si3_iwmmxt
+ : fcode == ARM_BUILTIN_WSRAD ? CODE_FOR_ashrdi3_di
+ : fcode == ARM_BUILTIN_WSRADI ? CODE_FOR_ashrdi3_iwmmxt
+ : fcode == ARM_BUILTIN_WSRLH ? CODE_FOR_lshrv4hi3_di
+ : fcode == ARM_BUILTIN_WSRLHI ? CODE_FOR_lshrv4hi3_iwmmxt
+ : fcode == ARM_BUILTIN_WSRLW ? CODE_FOR_lshrv2si3_di
+ : fcode == ARM_BUILTIN_WSRLWI ? CODE_FOR_lshrv2si3_iwmmxt
+ : fcode == ARM_BUILTIN_WSRLD ? CODE_FOR_lshrdi3_di
+ : fcode == ARM_BUILTIN_WSRLDI ? CODE_FOR_lshrdi3_iwmmxt
+ : fcode == ARM_BUILTIN_WRORH ? CODE_FOR_rorv4hi3_di
+ : fcode == ARM_BUILTIN_WRORHI ? CODE_FOR_rorv4hi3
+ : fcode == ARM_BUILTIN_WRORW ? CODE_FOR_rorv2si3_di
+ : fcode == ARM_BUILTIN_WRORWI ? CODE_FOR_rorv2si3
+ : fcode == ARM_BUILTIN_WRORD ? CODE_FOR_rordi3_di
+ : fcode == ARM_BUILTIN_WRORDI ? CODE_FOR_rordi3
+ : fcode == ARM_BUILTIN_WAND ? CODE_FOR_iwmmxt_anddi3
+ : fcode == ARM_BUILTIN_WANDN ? CODE_FOR_iwmmxt_nanddi3
+ : fcode == ARM_BUILTIN_WOR ? CODE_FOR_iwmmxt_iordi3
+ : fcode == ARM_BUILTIN_WXOR ? CODE_FOR_iwmmxt_xordi3
+ : CODE_FOR_rordi3);
+ return arm_expand_binop_builtin (icode, exp, target);
+
case ARM_BUILTIN_WZERO:
target = gen_reg_rtx (DImode);
emit_insn (gen_iwmmxt_clrdi (target));
--
1.7.3.4