Re: [PATCH] More improvements to sparc VIS vec_init code generation.

[David Miller <davem at davemloft dot net>]

From: Eric Botcazou <ebotcazou@adacore.com>
Date: Wed, 9 Nov 2011 17:41:36 +0100

> There isn't an equivalent for 32-bit, is it?  That is, you can load 8, 16 and 
> 64 bits in the upper FP regs, but not 32 bits?

Indeed, you need to use normal 32-bit loads and thus the lower 32
float regs.

BTW, I suspect the paradoxical subreg trick will work without
pessimizing as long as you emit a clobber first.

Thanks for looking into the 64-bit failures, and actually if you want
I can work on fixing them myself this afternoon.