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Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order
- From: Uros Bizjak <ubizjak at gmail dot com>
- To: Kirill Yukhin <kirill dot yukhin at gmail dot com>
- Cc: "H.J. Lu" <hjl dot tools at gmail dot com>, gcc-patches List <gcc-patches at gcc dot gnu dot org>
- Date: Wed, 19 Oct 2011 15:21:50 +0200
- Subject: Re: [PATCH, i386, PR50766] Fix incorrect mem/reg operands order
- References: <CAGs3RfsRA3sKRUNhj2ABqvPm+HTXGga9rA=ZfgXL3YWaPVF+Gw@mail.gmail.com>
On Wed, Oct 19, 2011 at 3:07 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Here is (almost obvous) patch, which fixes PR50766.
>
> ChangeLog ?entry:
> 2011-10-19 ?Kirill Yukhin ?<kirill.yukhin@intel.com>
>
> ? ? ? ?* config/i386/i386.md (bmi_bextr_<mode>): Update register/
> ? ? ? ?memory operand order.
> ? ? ? ?(bmi2_bzhi_<mode>3): Ditto.
> ? ? ? ?(bmi2_pdep_<mode>3): Ditto.
> ? ? ? ?(bmi2_pext_<mode>3): Ditto.
>
> Bootstrapped, test (from bug) passing.
>
> Could you please have a look?
Please also add the testcase from the PR. You can use { dg-do
assemble }, but you have to check for BMI2 effective target support.
BTW: I can't find BMI2 instruction reference documentation, so I'm
just rubberstamping the patch as obvious.
So, OK with the testcase.
Thanks,
Uros.