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Re: [Patch 1/5] ARM 64 bit sync atomic operations [V3]


On 6 October 2011 18:51, Dr. David Alan Gilbert
<david.gilbert@linaro.org> wrote:
> ? ? ? gcc/
> ? ? ? * config/arm/arm.c (TARGET_HAVE_DMB_MCR): MCR Not available in Thumb1

Hasn't this been approved ? Please commit this.


cheers
Ramana

>
> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
> index 993e3a0..f6f1da7 100644
> --- a/gcc/config/arm/arm.h
> +++ b/gcc/config/arm/arm.h
> @@ -288,7 +288,8 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
> ?#define TARGET_HAVE_DMB ? ? ? ? ? ? ? ?(arm_arch7)
>
> ?/* Nonzero if this chip implements a memory barrier via CP15. ?*/
> -#define TARGET_HAVE_DMB_MCR ? ?(arm_arch6k && ! TARGET_HAVE_DMB)
> +#define TARGET_HAVE_DMB_MCR ? ?(arm_arch6 && ! TARGET_HAVE_DMB \
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?&& ! TARGET_THUMB1)
>
> ?/* Nonzero if this chip implements a memory barrier instruction. ?*/
> ?#define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR)
>


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