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Re: ARM 64-bit shift ICE


On 19/09/11 10:12, Paul Brook wrote:
In Thumb-2 mode we try and match an "M" constraint (const_int between 0 and
31) with no other alternatives. This fails, and with nowhere else to go we
ICE.

The fix is to restrict the predicate for these insns to only accept valid
const_int shift counts.  This prevents combine forming the shift-or insn, and
we proceed as before.

This is the exact same problem I've been trying to fix here:


http://gcc.gnu.org/ml/gcc-patches/2011-09/msg00049.html

The fix was initially rejected for not being restrictive enough, and then my predicate patch was rejected because Richard Sandiford pointed out that the predicate must not be more restrictive than the constraints or else reload may introduce recog ICE.

I believe your patch has the exact same problem.

I didn't get around to fixing both problems satisfactorily yet, but I have something cooking.

Andrew


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