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Re: [PATCH, ARM] Avoid element-order-dependent operations for quad-word vectors in big-endian mode for NEON
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: Julian Brown <julian at codesourcery dot com>
- Cc: gcc-patches at gcc dot gnu dot org, "Joseph S. Myers" <joseph at codesourcery dot com>, paul at codesourcery dot com
- Date: Thu, 30 Jun 2011 14:15:37 +0100
- Subject: Re: [PATCH, ARM] Avoid element-order-dependent operations for quad-word vectors in big-endian mode for NEON
- References: <20101209140551.50118914@rex.config> <Pine.LNX.4.64.1012091439240.22364@digraph.polyomino.org.uk> <20101209145639.4b16d7d1@rex.config> <20110112173822.052d18bb@rex.config>
On 12/01/11 17:38, Julian Brown wrote:
> On Thu, 9 Dec 2010 14:56:39 +0000
> Julian Brown <julian@codesourcery.com> wrote:
>
>> On Thu, 9 Dec 2010 14:40:59 +0000 (UTC)
>> "Joseph S. Myers" <joseph@codesourcery.com> wrote:
>>
>>> On Thu, 9 Dec 2010, Julian Brown wrote:
>>>
>>>> Unfortunately for C only, since building C++ was broken at the
>>>> time I started testing. Some tests fail to vectorize post-patch
>>>> in BE mode (predictably, since fewer things end up vectorizable),
>>>> but many execution tests transition from FAIL to PASS.
>>>
>>> Do any tests (scan, not execution) now fail for big endian in ways
>>> that indicate some of the check_effective_target_vect_* functions
>>> in target-supports.exp should be updated to know that certain
>>> features are only supported for little endian?
>>
>> Possibly, yes: I suspect a few of those may need updating, really. One
>> awkward bit is that I'm still allowing some of the operations for
>> double-word registers only -- I don't think the
>> check_effective_target_* tests will suffice to distinguish between
>> D-reg & Q-reg cases.
>
> This version of the patch tweaks target-supports.exp to say that
> various operations are not available in big-endian mode (removing some
> of the FAILs from the previous version -- though in big-endian mode
> without -mvectorize-with-neon-quad, some tests have transitioned from
> PASS to XPASS. I'm not sure that's worth worrying about).
>
> The main part of the patch remains unchanged.
>
> OK to apply?
>
> Cheers,
>
> Julian
>
> ChangeLog
>
> gcc/
> * config/arm/neon.md (vec_shr_<mode>, vec_shl_<mode>): Disable in
> big-endian mode.
> (reduc_splus_<mode>, reduc_uplus_<mode>, reduc_smin_<mode>)
> (reduc_smax_<mode>, reduc_umin_<mode>, reduc_umax_<mode>)
> (neon_vec_unpack<US>_lo_<mode>, neon_vec_unpack<US>_hi_<mode>)
> (vec_unpack<US>_hi_<mode>, vec_unpack<US>_lo_<mode>)
> (neon_vec_<US>mult_lo_<mode>, vec_widen_<US>mult_lo_<mode>)
> (neon_vec_<US>mult_hi_<mode>, vec_widen_<US>mult_hi_<mode>)
> (vec_pack_trunc_<mode>, neon_vec_pack_trunc_<mode>): Disable for Q
> registers in big-endian mode.
>
> gcc/testsuite/
> * lib/target-supports.exp
> (check_effective_target_arm_little_endian): New.
> (check_effective_target_vect_pack_trunc): Use above.
> (check_effective_target_vect_unpack): Likewise.
> (check_effective_target_vect_element_align): Test
> check_effective_target_arm_vect_no_misalign for ARM.
>
>
OK.
R.