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Re: [Patch, AVR]: Fix PR33049 (implement extzv)
Denis Chertykov schrieb:
> I'm vote for 'C'.
>
> Denis.
So it's C :-)
Johann
PR target/33049
* config/avr/avr.md (extzv): New expander.
(*extzv): New insn.
(*extzv.qihi1, *extzv.qihi2): New insn-and-split.
* config/avr/constraints.md (C04): New constraint.
* doc/md.texi (Machine Constraints): Document it.
Index: doc/md.texi
===================================================================
--- doc/md.texi (revision 175264)
+++ doc/md.texi (working copy)
@@ -1773,6 +1773,9 @@ Integer constant in the range @minus{}6
@item Q
A memory address based on Y or Z pointer with displacement.
+
+@item C04
+Constant integer 4
@end table
@item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
Index: config/avr/constraints.md
===================================================================
--- config/avr/constraints.md (revision 175201)
+++ config/avr/constraints.md (working copy)
@@ -107,3 +107,8 @@ (define_memory_constraint "Q"
"A memory address based on Y or Z pointer with displacement."
(and (match_code "mem")
(match_test "extra_constraint_Q (op)")))
+
+(define_constraint "C04"
+ "Constant integer 4."
+ (and (match_code "const_int")
+ (match_test "ival == 4")))
Index: config/avr/avr.md
===================================================================
--- config/avr/avr.md (revision 175264)
+++ config/avr/avr.md (working copy)
@@ -3539,3 +3539,65 @@ (define_insn_and_split "*ior<mode>qi.byt
int byteno = INTVAL(operands[2]) / BITS_PER_UNIT;
operands[4] = simplify_gen_subreg (QImode, operands[0], <MODE>mode, byteno);
})
+
+(define_expand "extzv"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (zero_extract:QI (match_operand:QI 1 "register_operand" "")
+ (match_operand:QI 2 "const1_operand" "")
+ (match_operand:QI 3 "const_0_to_7_operand" "")))]
+ ""
+ "")
+
+(define_insn "*extzv"
+ [(set (match_operand:QI 0 "register_operand" "=*d,*d,*d,*d,r")
+ (zero_extract:QI (match_operand:QI 1 "register_operand" "0,r,0,0,r")
+ (const_int 1)
+ (match_operand:QI 2 "const_0_to_7_operand" "L,L,P,C04,n")))]
+ ""
+ "@
+ andi %0,1
+ mov %0,%1\;andi %0,1
+ lsr %0\;andi %0,1
+ swap %0\;andi %0,1
+ bst %1,%2\;clr %0\;bld %0,0"
+ [(set_attr "length" "1,2,2,2,3")
+ (set_attr "cc" "set_zn,set_zn,set_zn,set_zn,clobber")])
+
+(define_insn_and_split "*extzv.qihi1"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (zero_extract:HI (match_operand:QI 1 "register_operand" "r")
+ (const_int 1)
+ (match_operand:QI 2 "const_0_to_7_operand" "n")))]
+ ""
+ "#"
+ ""
+ [(set (match_dup 3)
+ (zero_extract:QI (match_dup 1)
+ (const_int 1)
+ (match_dup 2)))
+ (set (match_dup 4)
+ (const_int 0))]
+ {
+ operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
+ operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
+ })
+
+(define_insn_and_split "*extzv.qihi2"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (zero_extend:HI
+ (zero_extract:QI (match_operand:QI 1 "register_operand" "r")
+ (const_int 1)
+ (match_operand:QI 2 "const_0_to_7_operand" "n"))))]
+ ""
+ "#"
+ ""
+ [(set (match_dup 3)
+ (zero_extract:QI (match_dup 1)
+ (const_int 1)
+ (match_dup 2)))
+ (set (match_dup 4)
+ (const_int 0))]
+ {
+ operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 0);
+ operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
+ })