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Hi Carrot,You are right. Now the logic is much clearer by splitting the constraints.
How about adding an alternative only enabled for T2 that uses the `l' constraint and inventing new constraints for some of the constant values that are valid for 16 bit instructions since the `I' and `L' constraints have different meanings depending on whether TARGET_32BIT is valid or not ? We could then set the value of the length attribute accordingly. I don't think we can change the meaning of the I and L constraints very easily given the amount of churn that might be needed
(define_insn "*arm_cmpsi_insn" [(set (reg:CC CC_REGNUM) - (compare:CC (match_operand:SI 0 "s_register_operand" "r,r") - (match_operand:SI 1 "arm_add_operand" "rI,L")))] + (compare:CC (match_operand:SI 0 "s_register_operand" "l,r,r,r") + (match_operand:SI 1 "arm_add_operand" "Py,r,I,L")))] "TARGET_32BIT" "@ cmp%?\\t%0, %1 + cmp%?\\t%0, %1 + cmp%?\\t%0, %1 cmn%?\\t%0, #%n1" - [(set_attr "conds" "set")] + [(set_attr "conds" "set")
(set_attr "arch" "t2, any") (set_attr "length" "2, 4")]
I don't think this and the other conditional branch instruction changes are correct. This could end up being the last instruction in an IT block and will automatically end up getting the 32 bit encoding and end up causing trouble with the length calculations. Remember the 16 bit encoding for the conditional instruction can't be used as the last instruction in an IT block.
According to arm architecture reference manual, chapter A8.6.16, neither 16 bit nor 32 bit conditional branch can be used in IT block. Only unconditional branch can be used as the last instruction in IT block, and it isn't related to instruction length. So we don't need to care about branch instruction encoding in IT block.
cheers Ramana
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