This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

PATCH: PR middle-end/47449: [x3 2] canât find a register in class âDIREG â while reloading âasmâ


Hi,

fwprop propagates zero/sign extended hard registers while not propagating 
hard registers in propagate_rtx. This patch avoids propagating zero/sign
extended hard registers.  OK for 4.7?

Thanks.


H.J.
---
commit 9fe3f4242e370b5728223e4198eb34b82eaa7e33
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Mon Jan 24 18:11:35 2011 -0800

    Don't propagate zero/sign extended hard register.

diff --git a/gcc/ChangeLog.x32 b/gcc/ChangeLog.x32
index ebe1d13..761799f 100644
--- a/gcc/ChangeLog.x32
+++ b/gcc/ChangeLog.x32
@@ -1,5 +1,11 @@
 2011-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 
+	PR middle-end/47449
+	* fwprop.c (forward_propagate_subreg): Don't propagate zero/sign
+	extended hard register.
+
+2011-01-24  H.J. Lu  <hongjiu.lu@intel.com>
+
 	PR target/47446
 	* config/i386/i386.c (ix86_output_addr_vec_elt): Check
 	TARGET_LP64 instead of TARGET_64BIT for ASM_QUAD.
diff --git a/gcc/fwprop.c b/gcc/fwprop.c
index 7ff5135..866cbe3 100644
--- a/gcc/fwprop.c
+++ b/gcc/fwprop.c
@@ -1119,6 +1119,7 @@ forward_propagate_subreg (df_ref use, rtx def_insn, rtx def_set)
       if ((GET_CODE (src) == ZERO_EXTEND
 	   || GET_CODE (src) == SIGN_EXTEND)
 	  && REG_P (XEXP (src, 0))
+	  && REGNO (XEXP (src, 0)) >= FIRST_PSEUDO_REGISTER
 	  && GET_MODE (XEXP (src, 0)) == use_mode
 	  && !free_load_extend (src, def_insn)
 	  && all_uses_available_at (def_insn, use_insn))
diff --git a/gcc/testsuite/ChangeLog.x32 b/gcc/testsuite/ChangeLog.x32
index 506585d..271a2ae 100644
--- a/gcc/testsuite/ChangeLog.x32
+++ b/gcc/testsuite/ChangeLog.x32
@@ -1,5 +1,10 @@
 2011-01-24  H.J. Lu  <hongjiu.lu@intel.com>
 
+	PR middle-end/47449
+	* gcc.target/i386/pr47449.c: New.
+
+2011-01-24  H.J. Lu  <hongjiu.lu@intel.com>
+
 	PR target/47446
 	* gcc.target/i386/pr47446-1.c: New.
 
diff --git a/gcc/testsuite/gcc.target/i386/pr47449.c b/gcc/testsuite/gcc.target/i386/pr47449.c
new file mode 100644
index 0000000..99ef32f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr47449.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+void bar (void *, void *);
+int
+foo (void *p1, void *p2)
+{
+  int ret1, ret2;
+  __asm ("" : "=D" (ret1), "=S" (ret2));
+  bar (p1, p2);
+  return ret1 + ret2;
+}


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]