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Re: [RFC ARM] Fix PR43721 - combine multiple div and mod into a single divmod call.
- From: Richard Henderson <rth at redhat dot com>
- To: Ramana Radhakrishnan <ramana dot gcc at googlemail dot com>
- Cc: gcc-patches <gcc-patches at gcc dot gnu dot org>, Richard Earnshaw <rearnsha at arm dot com>
- Date: Sun, 23 Jan 2011 14:49:08 -0800
- Subject: Re: [RFC ARM] Fix PR43721 - combine multiple div and mod into a single divmod call.
- References: <AANLkTinnRCXxgVGO3OrGxmMc7G+UVPV3EtS0q99Osmpr@mail.gmail.com>
On 01/21/2011 04:37 PM, Ramana Radhakrishnan wrote:
> +(define_insn_and_split "divmodsi4"
> + [(parallel [(set (match_operand:SI 0 "s_register_operand" "")
> + (div:SI (match_operand:SI 1 "s_register_operand" "")
> + (match_operand:SI 2 "s_register_operand" "")))
> + (set (match_operand:SI 3 "s_register_operand" "")
> + (mod:SI (match_dup 1) (match_dup 2)))
> + (clobber (reg:SI 0))
> + (clobber (reg:SI 1))
> + (clobber (reg:SI LR_REGNUM))])]
define_insn, unlike define_expand, has an implicit parallel.
You've got a redundant parallel in there.
> + ""
> + "#"
> + "!(TARGET_THUMB2 && arm_arch_hwdiv)"
You have an unconditional insn, that is must-split, with a conditional
split? That seems very wrong. I suspect you want that condition moved
to the first "".
> +(define_insn "aeabi_divsi3_call"
> + [(set (reg:SI 0) (div:SI (reg:SI 0) (reg:SI 1)))
> + (clobber (reg:SI LR_REGNUM))]
> + "!(TARGET_THUMB2 && arm_arch_hwdiv)"
> + "bl\t__aeabi_idiv"
> + [(set_attr "type" "call")
> + (set_attr "conds" "clob")])
Does the eabi really say that no register except r0 is modified?
That doesn't seem to be the case, based on a quick glance over
the implementation in lib1funcs.asm.
If that's the case, your representation is very wrong.
r~