[testsuite] Add -msse to all i386 vector tests (PR target/46280)

[Rainer Orth <ro at CeBiTec dot Uni-Bielefeld dot DE>]

This patch is a first attempt to fix PR target/46280: on Solaris 8 and
9/x86, the compiler defaults to -march=pentiumpro, so all vector tests
FAIL due to this warning:

+FAIL: g++.dg/eh/simd-2.C (test for excess errors)

Excess errors:
/vol/gcc/src/hg/trunk/local/gcc/testsuite/g++.dg/eh/simd-2.C:13:8: note: The
ABI of passing parameter with 16byte alignment has changed in GCC 4.6

Btw, it seems like the message should read `16-byte alignement' (with a
dash) instead, and perhaps `ABI for passing' would be better as well.

As requested by Uros, I'm adding -msse to all affected tests.  The
dejagnu directives are syntactically valid, as checked with manual
runtest invocations, and with one exception the tests now pass on
i386-pc-solaris2.9.

I've moved the three files in gcc.c-torture/execute to gcc.dg/execute
since I cannot use dg-* directives in the former directory and handling
this with .x files is sort of ugly.  I know moving testcases is frowned
upon, but this seems to be a valid case.

gcc.target/i386/vect-args.c still fails because the testcase is cycled
through several options and only passes with -msse2.  Adding -msse
obviously doesn't help.  I'm not sure what the best way to handle this
is.

Apart from this, I've not run a full bootstrap, especially not on a
platform that lacks SSE support in the assembler.  In this case,
dg-options wouldn't work as is, but one could change the tests into
assemble tests instead of compile tests.

Comments?

	Rainer


2010-11-05  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	PR target/46280
	* gcc/testsuite/g++.dg/eh/simd-2.C: Add -msse to dg-options, add
	dg-require-effective-target sse_runtime for for i?86-*-*, x86_64-*-*.
	* gcc/testsuite/g++.dg/torture/pr36444.C: Add dg-options -msse for
	i?86-*-* x86_64-*-*.
	* g++.dg/torture/pr36445.C: Likewise.
	* gcc.c-torture/compile/pr34856.c: Likewise.
	* gcc.c-torture/compile/pr39928-1.c: Likewise.
	* gcc.c-torture/compile/vector-1.c: Likewise.
	* gcc.c-torture/compile/vector-2.c: Likewise.
	* gcc.dg/pr32912-1.c: Likewise.
	* gcc.c-torture/execute/va-arg-25.c: Move ...
	* gcc.dg/torture/va-arg-25.c: ... here.
	Add dg-do run.
	Add dg-options -msse, dg-require-effective-target sse_runtime for
	for i?86-*-*, x86_64-*-*.
	* gcc.c-torture/execute/vector-1.c: Likewise.
	* gcc.c-torture/execute/vector-2.c: Likewise.
	* gcc.dg/tree-ssa/forwprop-5.c: Add -msse to dg-options for
	i?86-*-*, x86_64-*-*.
	* gcc.dg/tree-ssa/fre-vce-1.c: Likewise.
	* gcc.dg/tree-ssa/sra-4.c: Likewise.
	* gcc.dg/tree-ssa/vector-1.c: Likewise.
	* gcc.dg/tree-ssa/vector-2.c: Likewise.
	* gcc.target/i386/vect-args.c: Likewise.

diff -r 15655a07238e gcc/testsuite/g++.dg/eh/simd-2.C
--- a/gcc/testsuite/g++.dg/eh/simd-2.C	Fri Nov 05 20:12:32 2010 +0100
+++ b/gcc/testsuite/g++.dg/eh/simd-2.C	Fri Nov 05 20:26:36 2010 +0100
@@ -1,10 +1,11 @@
 // Test EH when V4SI SIMD registers are involved.
 // Contributed by Aldy Hernandez (aldy@quesejoda.com).
 // { dg-options "-O -Wno-abi" }
-// { dg-options "-O -w" { target { { i?86-*-* x86_64-*-* } && ilp32 } } }
+// { dg-options "-O -w -msse" { target { { i?86-*-* x86_64-*-* } && ilp32 } } }
 // { dg-options "-O -w" { target powerpc*-*-* } }
 // { dg-options "-O -w -maltivec" { target { powerpc*-*-* && vmx_hw } } }
 // { dg-do run }
+// { dg-require-effective-target sse_runtime { target { { i?86-*-* x86_64-*-* } && ilp32 } } }
 
 #include "check-vect.h"
 
diff -r 15655a07238e gcc/testsuite/g++.dg/torture/pr36444.C
--- a/gcc/testsuite/g++.dg/torture/pr36444.C	Fri Nov 05 20:12:32 2010 +0100
+++ b/gcc/testsuite/g++.dg/torture/pr36444.C	Fri Nov 05 20:26:36 2010 +0100
@@ -1,4 +1,5 @@
 /* { dg-do compile } */
+/* { dg-options "-msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
 #define vector __attribute__((vector_size(16) ))
 struct struct1  {
   union {}    vmx;
diff -r 15655a07238e gcc/testsuite/g++.dg/torture/pr36445.C
--- a/gcc/testsuite/g++.dg/torture/pr36445.C	Fri Nov 05 20:12:32 2010 +0100
+++ b/gcc/testsuite/g++.dg/torture/pr36445.C	Fri Nov 05 20:26:36 2010 +0100
@@ -1,4 +1,5 @@
 /* { dg-do compile } */
+/* { dg-options "-msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
 // This used to fail as we would try to expand a VCE where one side had
 // a mode of BLKmode and the other side was a vector mode.
 #define vector __attribute__((vector_size(16) ))
diff -r 15655a07238e gcc/testsuite/gcc.c-torture/compile/pr34856.c
--- a/gcc/testsuite/gcc.c-torture/compile/pr34856.c	Fri Nov 05 20:12:32 2010 +0100
+++ b/gcc/testsuite/gcc.c-torture/compile/pr34856.c	Fri Nov 05 20:26:36 2010 +0100
@@ -1,3 +1,4 @@
+/* { dg-options "-msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
 #undef __vector
 #define __vector __attribute__((vector_size(16) ))
 typedef __vector signed char qword;
diff -r 15655a07238e gcc/testsuite/gcc.c-torture/compile/pr39928-1.c
--- a/gcc/testsuite/gcc.c-torture/compile/pr39928-1.c	Fri Nov 05 20:12:32 2010 +0100
+++ b/gcc/testsuite/gcc.c-torture/compile/pr39928-1.c	Fri Nov 05 20:26:36 2010 +0100
@@ -1,3 +1,4 @@
+/* { dg-options "-msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
 typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
 extern __m128 _mm_sub_ps (__m128 __A, __m128 __B);
 extern __m128 _mm_mul_ps (__m128 __A, __m128 __B);
diff -r 15655a07238e gcc/testsuite/gcc.c-torture/compile/vector-1.c
--- a/gcc/testsuite/gcc.c-torture/compile/vector-1.c	Fri Nov 05 20:12:32 2010 +0100
+++ b/gcc/testsuite/gcc.c-torture/compile/vector-1.c	Fri Nov 05 20:26:36 2010 +0100
@@ -1,3 +1,4 @@
+/* { dg-options "-msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
 #define vector __attribute__((vector_size(16) ))
 struct ss
 {
diff -r 15655a07238e gcc/testsuite/gcc.c-torture/compile/vector-2.c
--- a/gcc/testsuite/gcc.c-torture/compile/vector-2.c	Fri Nov 05 20:12:32 2010 +0100
+++ b/gcc/testsuite/gcc.c-torture/compile/vector-2.c	Fri Nov 05 20:26:36 2010 +0100
@@ -1,3 +1,4 @@
+/* { dg-options "-msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
 #define vector __attribute__((vector_size(16) ))
 struct ss
 {
diff -r 15655a07238e gcc/testsuite/gcc.c-torture/execute/va-arg-25.c
--- a/gcc/testsuite/gcc.c-torture/execute/va-arg-25.c	Fri Nov 05 20:12:32 2010 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,37 +0,0 @@
-/* Varargs and vectors!  */
-
-#include <stdarg.h>
-#include <limits.h>
-
-#define vector __attribute__((vector_size(16)))
-
-const vector unsigned int v1 = {10,11,12,13};
-const vector unsigned int v2 = {20,21,22,23};
-
-void foo(int a, ...)
-{
-  va_list args;
-  vector unsigned int v;
-
-  va_start (args, a);
-  v = va_arg (args, vector unsigned int);
-  if (a != 1 || memcmp (&v, &v1, sizeof (v)) != 0)
-    abort ();
-  a = va_arg (args, int);
-  if (a != 2)
-    abort ();
-  v = va_arg (args, vector unsigned int);
-  if (memcmp (&v, &v2, sizeof (v)) != 0)
-    abort ();
-  va_end (args);
-}
-
-int main(void)
-{
-#if INT_MAX == 2147483647
-  foo (1, (vector unsigned int){10,11,12,13}, 2,
-       (vector unsigned int){20,21,22,23});
-#endif
-  return 0;
-}
-
diff -r 15655a07238e gcc/testsuite/gcc.c-torture/execute/vector-1.c
--- a/gcc/testsuite/gcc.c-torture/execute/vector-1.c	Fri Nov 05 20:12:32 2010 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,36 +0,0 @@
-/* Check that vector extraction works correctly. */
-
-#define vector __attribute__((vector_size(16) ))
-
-int f0(vector int t)
-{
-  return ((int*)&t)[0];
-}
-int f1(vector int t)
-{
-  return ((int*)&t)[1];
-}
-int f2(vector int t)
-{
-  return ((int*)&t)[2];
-}
-int f3(vector int t)
-{
-  return ((int*)&t)[3];
-}
-int main(void)
-{
-  vector int a = {0, 1, 2, 3};
-  /* Make sure that we have the correct size for the vectors. */
-  if (sizeof(int) != 4)
-    __builtin_exit (0);
-  if (f0(a) != 0)
-    __builtin_abort ();
-  if (f1(a) != 1)
-    __builtin_abort ();
-  if (f2(a) != 2)
-    __builtin_abort ();
-  if (f3(a) != 3)
-    __builtin_abort ();
-  return 0;
-}
diff -r 15655a07238e gcc/testsuite/gcc.c-torture/execute/vector-2.c
--- a/gcc/testsuite/gcc.c-torture/execute/vector-2.c	Fri Nov 05 20:12:32 2010 +0100
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,46 +0,0 @@
-/* Check that vector insertion works correctly. */
-
-#define vector __attribute__((vector_size(16) ))
-
-vector int f0(vector int t, int a)
-{
- ((int*)&t)[0] = a;
- return t;
-}
-vector int f1(vector int t, int a)
-{
- ((int*)&t)[1] = a;
- return t;
-}
-vector int f2(vector int t, int a)
-{
- ((int*)&t)[2] = a;
- return t;
-}
-vector int f3(vector int t, int a)
-{
- ((int*)&t)[3] = a;
- return t;
-}
-int main(void)
-{
-  vector int a = {0, 0, 0, 0};
-  vector int b = {1, 0, 0, 0};
-  vector int c = {0, 1, 0, 0};
-  vector int d = {0, 0, 1, 0};
-  vector int e = {0, 0, 0, 1};
-  vector int a0;
-  a0 = f0(a, 1);
-  if (memcmp (&a0, &b, sizeof(a0)))
-    __builtin_abort ();
-  a0 = f1(a, 1);
-  if (memcmp (&a0, &c, sizeof(a0)))
-    __builtin_abort ();
-  a0 = f2(a, 1);
-  if (memcmp (&a0, &d, sizeof(a0)))
-    __builtin_abort ();
-  a0 = f3(a, 1);
-  if (memcmp (&a0, &e, sizeof(a0)))
-    __builtin_abort ();
-  return 0;
-}
diff -r 15655a07238e gcc/testsuite/gcc.dg/pr32912-1.c
--- a/gcc/testsuite/gcc.dg/pr32912-1.c	Fri Nov 05 20:12:32 2010 +0100
+++ b/gcc/testsuite/gcc.dg/pr32912-1.c	Fri Nov 05 20:26:36 2010 +0100
@@ -2,6 +2,8 @@
 /* { dg-do run } */
 /* { dg-options "-O2 -w" } */
 /* { dg-options "-O2 -w -fno-common" { target hppa*-*-hpux* } } */
+/* { dg-options "-O2 -w -msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
+/* { dg-require-effective-target sse_runtime { target { i?86-*-* x86_64-*-* } } } */
 
 extern void abort (void);
 
diff -r 15655a07238e gcc/testsuite/gcc.dg/torture/va-arg-25.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gcc/testsuite/gcc.dg/torture/va-arg-25.c	Fri Nov 05 20:26:36 2010 +0100
@@ -0,0 +1,42 @@
+/* Varargs and vectors!  */
+
+/* { dg-do run } */
+/* { dg-options "-msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
+/* { dg-require-effective-target sse_runtime { target { i?86-*-* x86_64-*-* } } } */
+
+#include <stdarg.h>
+#include <stdlib.h>
+#include <limits.h>
+
+#define vector __attribute__((vector_size(16)))
+
+const vector unsigned int v1 = {10,11,12,13};
+const vector unsigned int v2 = {20,21,22,23};
+
+void foo(int a, ...)
+{
+  va_list args;
+  vector unsigned int v;
+
+  va_start (args, a);
+  v = va_arg (args, vector unsigned int);
+  if (a != 1 || memcmp (&v, &v1, sizeof (v)) != 0)
+    abort ();
+  a = va_arg (args, int);
+  if (a != 2)
+    abort ();
+  v = va_arg (args, vector unsigned int);
+  if (memcmp (&v, &v2, sizeof (v)) != 0)
+    abort ();
+  va_end (args);
+}
+
+int main(void)
+{
+#if INT_MAX == 2147483647
+  foo (1, (vector unsigned int){10,11,12,13}, 2,
+       (vector unsigned int){20,21,22,23});
+#endif
+  return 0;
+}
+
diff -r 15655a07238e gcc/testsuite/gcc.dg/torture/vector-1.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gcc/testsuite/gcc.dg/torture/vector-1.c	Fri Nov 05 20:26:36 2010 +0100
@@ -0,0 +1,40 @@
+/* Check that vector extraction works correctly. */
+
+/* { dg-do run } */
+/* { dg-options "-msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
+/* { dg-require-effective-target sse_runtime { target { i?86-*-* x86_64-*-* } } } */
+
+#define vector __attribute__((vector_size(16) ))
+
+int f0(vector int t)
+{
+  return ((int*)&t)[0];
+}
+int f1(vector int t)
+{
+  return ((int*)&t)[1];
+}
+int f2(vector int t)
+{
+  return ((int*)&t)[2];
+}
+int f3(vector int t)
+{
+  return ((int*)&t)[3];
+}
+int main(void)
+{
+  vector int a = {0, 1, 2, 3};
+  /* Make sure that we have the correct size for the vectors. */
+  if (sizeof(int) != 4)
+    __builtin_exit (0);
+  if (f0(a) != 0)
+    __builtin_abort ();
+  if (f1(a) != 1)
+    __builtin_abort ();
+  if (f2(a) != 2)
+    __builtin_abort ();
+  if (f3(a) != 3)
+    __builtin_abort ();
+  return 0;
+}
diff -r 15655a07238e gcc/testsuite/gcc.dg/torture/vector-2.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gcc/testsuite/gcc.dg/torture/vector-2.c	Fri Nov 05 20:26:36 2010 +0100
@@ -0,0 +1,50 @@
+/* Check that vector insertion works correctly. */
+
+/* { dg-do run } */
+/* { dg-options "-msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
+/* { dg-require-effective-target sse_runtime { target { i?86-*-* x86_64-*-* } } } */
+
+#define vector __attribute__((vector_size(16) ))
+
+vector int f0(vector int t, int a)
+{
+ ((int*)&t)[0] = a;
+ return t;
+}
+vector int f1(vector int t, int a)
+{
+ ((int*)&t)[1] = a;
+ return t;
+}
+vector int f2(vector int t, int a)
+{
+ ((int*)&t)[2] = a;
+ return t;
+}
+vector int f3(vector int t, int a)
+{
+ ((int*)&t)[3] = a;
+ return t;
+}
+int main(void)
+{
+  vector int a = {0, 0, 0, 0};
+  vector int b = {1, 0, 0, 0};
+  vector int c = {0, 1, 0, 0};
+  vector int d = {0, 0, 1, 0};
+  vector int e = {0, 0, 0, 1};
+  vector int a0;
+  a0 = f0(a, 1);
+  if (memcmp (&a0, &b, sizeof(a0)))
+    __builtin_abort ();
+  a0 = f1(a, 1);
+  if (memcmp (&a0, &c, sizeof(a0)))
+    __builtin_abort ();
+  a0 = f2(a, 1);
+  if (memcmp (&a0, &d, sizeof(a0)))
+    __builtin_abort ();
+  a0 = f3(a, 1);
+  if (memcmp (&a0, &e, sizeof(a0)))
+    __builtin_abort ();
+  return 0;
+}
diff -r 15655a07238e gcc/testsuite/gcc.dg/tree-ssa/forwprop-5.c
--- a/gcc/testsuite/gcc.dg/tree-ssa/forwprop-5.c	Fri Nov 05 20:12:32 2010 +0100
+++ b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-5.c	Fri Nov 05 20:26:36 2010 +0100
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-O1 -fdump-tree-optimized -w" } */
+/* { dg-options "-O1 -fdump-tree-optimized -w -msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
 
 #define vector __attribute__((vector_size(16) ))
 struct VecClass
diff -r 15655a07238e gcc/testsuite/gcc.dg/tree-ssa/fre-vce-1.c
--- a/gcc/testsuite/gcc.dg/tree-ssa/fre-vce-1.c	Fri Nov 05 20:12:32 2010 +0100
+++ b/gcc/testsuite/gcc.dg/tree-ssa/fre-vce-1.c	Fri Nov 05 20:26:36 2010 +0100
@@ -1,4 +1,5 @@
 /* { dg-options "-O2 -fdump-tree-fre -w" } */
+/* { dg-options "-O2 -fdump-tree-fre -w -msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
 /* { dg-do compile } */
 #define vector __attribute__((vector_size(sizeof(int)*4) ))
 struct s { vector int i; };
diff -r 15655a07238e gcc/testsuite/gcc.dg/tree-ssa/sra-4.c
--- a/gcc/testsuite/gcc.dg/tree-ssa/sra-4.c	Fri Nov 05 20:12:32 2010 +0100
+++ b/gcc/testsuite/gcc.dg/tree-ssa/sra-4.c	Fri Nov 05 20:26:36 2010 +0100
@@ -1,6 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-O1 -fdump-tree-optimized -w" } */
-/* Check that SRA replaces strucutres containing vectors. */
+/* { dg-options "-O1 -fdump-tree-optimized -w -msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
+/* Check that SRA replaces structures containing vectors. */
 
 #define vector __attribute__((vector_size(16)))
 
diff -r 15655a07238e gcc/testsuite/gcc.dg/tree-ssa/vector-1.c
--- a/gcc/testsuite/gcc.dg/tree-ssa/vector-1.c	Fri Nov 05 20:12:32 2010 +0100
+++ b/gcc/testsuite/gcc.dg/tree-ssa/vector-1.c	Fri Nov 05 20:26:36 2010 +0100
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-w -O1 -fdump-tree-gimple" } */
+/* { dg-options "-w -O1 -fdump-tree-gimple -msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
 
 
 /* We should be able to produce a BIT_FIELD_REF for each of these vector access. */
diff -r 15655a07238e gcc/testsuite/gcc.dg/tree-ssa/vector-2.c
--- a/gcc/testsuite/gcc.dg/tree-ssa/vector-2.c	Fri Nov 05 20:12:32 2010 +0100
+++ b/gcc/testsuite/gcc.dg/tree-ssa/vector-2.c	Fri Nov 05 20:26:36 2010 +0100
@@ -1,5 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-w -O1 -fdump-tree-optimized" } */
+/* { dg-options "-w -O1 -fdump-tree-optimized -msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
 
 #define vector __attribute__(( vector_size(16) ))
 
diff -r 15655a07238e gcc/testsuite/gcc.target/i386/vect-args.c
--- a/gcc/testsuite/gcc.target/i386/vect-args.c	Fri Nov 05 20:12:32 2010 +0100
+++ b/gcc/testsuite/gcc.target/i386/vect-args.c	Fri Nov 05 20:26:36 2010 +0100
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-w" } */
+/* { dg-options "-w -msse" { target { { i?86-*-* x86_64-*-* } && sse } } } */
 
 /* SSE1 and SSE2 modes.  */
 typedef unsigned char V16QImode __attribute__((vector_size(16)));


-- 
-----------------------------------------------------------------------------
Rainer Orth, Center for Biotechnology, Bielefeld University