Re: 0004-Model-Core-2-i7-decoder-bottleneck

[Uros Bizjak <ubizjak at gmail dot com>]

On Fri, Oct 29, 2010 at 9:32 PM, Vladimir Makarov <vmakarov@redhat.com> wrote:
> ?On 10/26/2010 10:20 AM, Maxim Kuvyrkov wrote:
>>
>> This patch makes the scheduler aware of decoder restrictions on Core 2/i7.
>> ?It adds new hooks to multipass scheduling that allow the target to filter
>> the search space from instructions that should not be tried in current
>> [partial] solution of multipass scheduling.
>>
>> The primary motivation of this patch is to model limited-size buffers,
>> such as decoder fetch blocks, and, more generally, CPU pipeline features
>> that are difficult to express in a DFA model. ?For Core 2/i7 we need to
>> model a 16-byte decoder buffer filled with variable-length instructions.
>> ?When the modelled buffer becomes nearly full the hooks remove instructions
>> that would not fit the rest of the buffer from multipass scheduler
>> consideration.
>>
>> The patch does not affect behavior of targets that do not define the new
>> hooks.
>>
>> The patch touches both i386 backend and the haifa scheduler; the i386 part
>> is at the beginning of the patch and the target-independent changes are in
>> the second part of the patch.
>>
>> Tested by bootstrapping on i686-pc-linux-gnu, an earlier version was
>> successfully regtested. ?The patch shows 0.1-0.25% performance improvement
>> on SPEC2000. ?I'm now rerunning the SPEC2000 and SPEC2006 benchmarks and
>> will post the final results in a day or so.
>>
>> Your approvals and comments are welcome.
>>
> I think the way you simulate the insns buffer would be even more interesting
> to AMD folks because AMD processors are usually more sensitive to insn
> scheduling than Intel ones.
>>
>> OK to commit?
>
> The scheduler part is ok for me. ?You just need to fix the typo in Changelog

The x86 part is also OK.

Thanks,
Uros.