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Re: 0004-Model-Core-2-i7-decoder-bottleneck
- From: Vladimir Makarov <vmakarov at redhat dot com>
- To: Maxim Kuvyrkov <maxim at codesourcery dot com>
- Cc: gcc-patches <gcc-patches at gcc dot gnu dot org>, Richard Henderson <rth at redhat dot com>, "H.J. Lu" <hongjiu dot lu at intel dot com>, Jan Hubicka <jh at suse dot cz>, Uros Bizjak <ubizjak at gmail dot com>, Bernd Schmidt <bernds at codesourcery dot com>
- Date: Fri, 29 Oct 2010 15:32:34 -0400
- Subject: Re: 0004-Model-Core-2-i7-decoder-bottleneck
- References: <4CBD7F43.3050209@codesourcery.com> <4CC6E3A4.9040105@codesourcery.com>
On 10/26/2010 10:20 AM, Maxim Kuvyrkov wrote:
This patch makes the scheduler aware of decoder restrictions on Core
2/i7. It adds new hooks to multipass scheduling that allow the target
to filter the search space from instructions that should not be tried
in current [partial] solution of multipass scheduling.
The primary motivation of this patch is to model limited-size buffers,
such as decoder fetch blocks, and, more generally, CPU pipeline
features that are difficult to express in a DFA model. For Core 2/i7
we need to model a 16-byte decoder buffer filled with variable-length
instructions. When the modelled buffer becomes nearly full the hooks
remove instructions that would not fit the rest of the buffer from
multipass scheduler consideration.
The patch does not affect behavior of targets that do not define the
new hooks.
The patch touches both i386 backend and the haifa scheduler; the i386
part is at the beginning of the patch and the target-independent
changes are in the second part of the patch.
Tested by bootstrapping on i686-pc-linux-gnu, an earlier version was
successfully regtested. The patch shows 0.1-0.25% performance
improvement on SPEC2000. I'm now rerunning the SPEC2000 and SPEC2006
benchmarks and will post the final results in a day or so.
Your approvals and comments are welcome.
I think the way you simulate the insns buffer would be even more
interesting to AMD folks because AMD processors are usually more
sensitive to insn scheduling than Intel ones.
OK to commit?
The scheduler part is ok for me. You just need to fix the typo in Changelog
* doc/tm.texi: Regenrate.
and add a sentence for TARGET_SCHED_FIRST_CYCLE_MULTIPASS_FINI in
document files (although its meaning is easy to guess from the context
and it is described in target.def). That is what I found.
Thanks for the patch, Maxim.