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0004-Model-Core-2-i7-decoder-bottleneck


This patch makes the scheduler aware of decoder restrictions on Core 2/i7. It adds new hooks to multipass scheduling that allow the target to filter the search space from instructions that should not be tried in current [partial] solution of multipass scheduling.

The primary motivation of this patch is to model limited-size buffers, such as decoder fetch blocks, and, more generally, CPU pipeline features that are difficult to express in a DFA model. For Core 2/i7 we need to model a 16-byte decoder buffer filled with variable-length instructions. When the modelled buffer becomes nearly full the hooks remove instructions that would not fit the rest of the buffer from multipass scheduler consideration.

The patch does not affect behavior of targets that do not define the new hooks.

The patch touches both i386 backend and the haifa scheduler; the i386 part is at the beginning of the patch and the target-independent changes are in the second part of the patch.

Tested by bootstrapping on i686-pc-linux-gnu, an earlier version was successfully regtested. The patch shows 0.1-0.25% performance improvement on SPEC2000. I'm now rerunning the SPEC2000 and SPEC2006 benchmarks and will post the final results in a day or so.

Your approvals and comments are welcome.

OK to commit?

Thank you,

--
Maxim Kuvyrkov
CodeSourcery
maxim@codesourcery.com
(650) 331-3385 x724

Attachment: 0004-Model-Core-2-i7-decoder-bottleneck.ChangeLog
Description: Text document

Attachment: 0004-Model-Core-2-i7-decoder-bottleneck.patch
Description: Text document


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