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Re: Patch for AMD Dispatch Scheduler
- From: Richard Henderson <rth at redhat dot com>
- To: reza yazdani <yazdani_reza at yahoo dot com>
- Cc: gcc-patches at gcc dot gnu dot org, jh at suse dot cz, ubizjak at gmail dot com, vmakarov at redhat dot com, sebpop at gmail dot com
- Date: Mon, 16 Aug 2010 16:14:23 -0700
- Subject: Re: Patch for AMD Dispatch Scheduler
- References: <886108.82044.qm@web33007.mail.mud.yahoo.com>
On 08/12/2010 05:27 PM, reza yazdani wrote:
> The scheduling part (this patch) arranges instructions to maximize
> the throughput of the hardware dispatcher. It makes sure dispatch
> widow boundaries are roughly observed. It is roughly, because the
> lengths of instructions, in number of bytes, are not known at the
> scheduling time. In x86 some instruction lengths may not be known
> until assembly time where information such as branch offsets are
> computed. Scheduling part is called once before register allocation
> and once after register allocation.
I'm a bit confused how this "dispatch" scheduling is different
from other scheduling, and why it needs so many new hooks. The
whole process smells very similar to "bundling" like we'd do on
ia64 for instance.
For instance, if I compare the structure of your new
ready_remove_first_dispatch function to choose_ready, I see
many similarities. It sure looks like the multipass_dfa
scheduling hooks can be made to do what you want.
Can you explain what's fundamentally different about your bits?
r~