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Re: [vect] Ask for review and approving the patch about vect and loongson
- From: Mingjie Xing <mingjie dot xing at gmail dot com>
- To: rdsandiford at googlemail dot com, richard dot guenther at gmail dot com, gcc-patches at gcc dot gnu dot org
- Date: Fri, 13 Aug 2010 13:59:06 +0800
- Subject: Re: [vect] Ask for review and approving the patch about vect and loongson
Hello,
> Eric Fisher <joefoxreal@gmail.com> writes:
>> Thanks. I've updated the patch in the attachment.
>
> Watch the formatting: the (match_operand: ...)s should line up vertically.
>
> The patch is OK with that change. Obviously we'll have to wait until
> the copyright assignment is sorted out before the patches can be applied.
>
> Richard
>
My GCC assignment/disclaimer process with the FSF is currently
complete. I've put the previously reviewed patches in the attachment
and changed the contact also.
Mingjie Xing <mingjie.xing@gmail.com>
gcc/ChangeLog
* loongson.md: Change define_insn "loongson_pmull<V_suffix>" to "mul<mode>3".
* mips.c: Add "#define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3".
testsuite/ChangeLog
* fast-math-vect-reduc-8.c: Move dg-require-effective-target after dg-do.
* vect.exp: Run the vect testsuite when the target is loongson*
* target-supports.exp: Check loongson target in vector specific attributes.
BTW, I don't have write access to svn.
Regards,
Mingjie
Index: config/mips/loongson.md
===================================================================
--- config/mips/loongson.md (revision 163219)
+++ config/mips/loongson.md (working copy)
@@ -31,7 +31,6 @@
UNSPEC_LOONGSON_PMOVMSK
UNSPEC_LOONGSON_PMULHU
UNSPEC_LOONGSON_PMULH
- UNSPEC_LOONGSON_PMULL
UNSPEC_LOONGSON_PMULU
UNSPEC_LOONGSON_PASUBUB
UNSPEC_LOONGSON_BIADD
@@ -353,11 +352,10 @@
[(set_attr "type" "fmul")])
;; Multiply signed integers and store low result.
-(define_insn "loongson_pmull<V_suffix>"
+(define_insn "mul<mode>3"
[(set (match_operand:VH 0 "register_operand" "=f")
- (unspec:VH [(match_operand:VH 1 "register_operand" "f")
- (match_operand:VH 2 "register_operand" "f")]
- UNSPEC_LOONGSON_PMULL))]
+ (mult:VH (match_operand:VH 1 "register_operand" "f")
+ (match_operand:VH 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
"pmull<V_suffix>\t%0,%1,%2"
[(set_attr "type" "fmul")])
Index: config/mips/mips.c
===================================================================
--- config/mips/mips.c (revision 163219)
+++ config/mips/mips.c (working copy)
@@ -12684,6 +12684,7 @@ AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BU
#define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
#define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
#define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
+#define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
#define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
#define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
#define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
Index: testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c
===================================================================
--- testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c (revision 163219)
+++ testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c (working copy)
@@ -1,5 +1,5 @@
-/* { dg-require-effective-target vect_float } */
/* { dg-do compile } */
+/* { dg-require-effective-target vect_float } */
#include "tree-vect.h"
Index: testsuite/gcc.dg/vect/vect.exp
===================================================================
--- testsuite/gcc.dg/vect/vect.exp (revision 163219)
+++ testsuite/gcc.dg/vect/vect.exp (working copy)
@@ -74,9 +74,12 @@ if [istarget "powerpc-*paired*"] {
set dg-do-what-default compile
}
} elseif { [istarget "mips*-*-*"]
- && [check_effective_target_mpaired_single]
- && [check_effective_target_nomips16] } {
- lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+ && ([check_effective_target_mpaired_single]
+ || [check_effective_target_mips_loongson])
+ && [check_effective_target_nomips16] } {
+ if { [check_effective_target_mpaired_single] } {
+ lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+ }
set dg-do-what-default run
} elseif [istarget "sparc*-*-*"] {
lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
Index: testsuite/lib/target-supports.exp
===================================================================
--- testsuite/lib/target-supports.exp (revision 163219)
+++ testsuite/lib/target-supports.exp (working copy)
@@ -1620,7 +1620,9 @@ proc check_effective_target_vect_int { }
|| [istarget sparc*-*-*]
|| [istarget alpha*-*-*]
|| [istarget ia64-*-*]
- || [check_effective_target_arm32] } {
+ || [check_effective_target_arm32]
+ || ([istarget mips*-*-*]
+ && [check_effective_target_mips_loongson]) } {
set et_vect_int_saved 1
}
}
@@ -2156,7 +2158,9 @@ proc check_effective_target_vect_shift {
|| [istarget ia64-*-*]
|| [istarget i?86-*-*]
|| [istarget x86_64-*-*]
- || [check_effective_target_arm32] } {
+ || [check_effective_target_arm32]
+ || ([istarget mips*-*-*]
+ && [check_effective_target_mips_loongson]) } {
set et_vect_shift_saved 1
}
}
@@ -2270,7 +2274,9 @@ proc check_effective_target_vect_no_int_
set et_vect_no_int_max_saved 0
if { [istarget sparc*-*-*]
|| [istarget spu-*-*]
- || [istarget alpha*-*-*] } {
+ || [istarget alpha*-*-*]
+ || ([istarget mips*-*-*]
+ && [check_effective_target_mips_loongson]) } {
set et_vect_no_int_max_saved 1
}
}
@@ -2643,7 +2649,9 @@ proc check_effective_target_vect_no_alig
if { [istarget mipsisa64*-*-*]
|| [istarget sparc*-*-*]
|| [istarget ia64-*-*]
- || [check_effective_target_arm32] } {
+ || [check_effective_target_arm32]
+ || ([istarget mips*-*-*]
+ && [check_effective_target_mips_loongson]) } {
set et_vect_no_align_saved 1
}
}
@@ -2833,8 +2841,10 @@ proc check_effective_target_vect_short_m
|| [istarget spu-*-*]
|| [istarget i?86-*-*]
|| [istarget x86_64-*-*]
- || [istarget powerpc*-*-*]
- || [check_effective_target_arm32] } {
+ || [istarget powerpc*-*-*]
+ || [check_effective_target_arm32]
+ || ([istarget mips*-*-*]
+ && [check_effective_target_mips_loongson]) } {
set et_vect_short_mult_saved 1
}
}