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[committed] Trivial tweak to gcc.target/mips/cache-1.c


It seems we now use 0(base) instead of 0x0(base) in the attached test.
TBH, I'm not sure when that changed, but...

Tested on mipsisa64-elfoabi and applied.

Richard


gcc/testsuite/
	* gcc.target/mips/cache-1.c: Allow 0 instead of 0x0.

Index: gcc/testsuite/gcc.target/mips/cache-1.c
===================================================================
--- gcc/testsuite/gcc.target/mips/cache-1.c	2010-07-17 10:31:06.000000000 +0100
+++ gcc/testsuite/gcc.target/mips/cache-1.c	2010-07-17 10:31:11.000000000 +0100
@@ -26,5 +26,5 @@ f4 (const volatile unsigned char *area)
 
 /* { dg-final { scan-assembler "\tcache\t0x14,0\\(\\\$4\\)" } } */
 /* { dg-final { scan-assembler "\tcache\t0x18,20\\(\\\$4\\)" } } */
-/* { dg-final { scan-assembler "\tcache\t0x0,0\\(\\\$.\\)" } } */
+/* { dg-final { scan-assembler "\tcache\t(0x|)0,0\\(\\\$.\\)" } } */
 /* { dg-final { scan-assembler "\tcache\t0x4,-80\\(\\\$4\\)" } } */


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