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[ARM] Fix reservation cortex_a8_load_store_2


I just found reservation cortex_a8_load_store_2 might not be correct. I think it should reserve cortex_a8_issue_ls in the second cycle. The patch is attached. I also add cortex_a8_issue_ls to the first cycle. So we can remove the comment on why we don't reserve cortex_a8_issue_ls. After the change, this reservation is not same as cortex_a8_multiply_2 any more. So I remove that comment, too.

Tested it on arm-none-eabi for NEON. Is it OK?


Regards, -- Jie Zhang CodeSourcery

	* config/arm/cortex-a8.md (cortex_a8_load_store_2): Reserve
	cortex_a8_issue_ls.

Index: config/arm/cortex-a8.md
===================================================================
--- config/arm/cortex-a8.md	(revision 162168)
+++ config/arm/cortex-a8.md	(working copy)
@@ -47,17 +47,15 @@
                     "(cortex_a8_alu0+cortex_a8_issue_ls)|\
                      (cortex_a8_alu1+cortex_a8_issue_ls)")
 
-;; ...and in the case of two micro-ops.  We don't need to reserve
-;; cortex_a8_issue_ls here because dual issue is altogether forbidden
+;; ...and in the case of two micro-ops.  Dual issue is altogether forbidden
 ;; during the issue cycle of the first micro-op.  (Instead of modelling
 ;; a separate issue unit, we instead reserve alu0 and alu1 to
 ;; prevent any other instructions from being issued upon that first cycle.)
 ;; Even though the load/store pipeline is usually available in either
-;; ALU pipe, multi-cycle instructions always issue in pipeline 0.  This
-;; reservation is therefore the same as cortex_a8_multiply_2 below.
+;; ALU pipe, multi-cycle instructions always issue in pipeline 0.
 (define_reservation "cortex_a8_load_store_2"
-                    "cortex_a8_alu0+cortex_a8_alu1,\
-                     cortex_a8_alu0")
+                    "cortex_a8_alu0+cortex_a8_alu1+cortex_a8_issue_ls,\
+                     cortex_a8_alu0+cortex_a8_issue_ls")
 
 ;; The flow of a single-cycle multiplication.
 (define_reservation "cortex_a8_multiply"


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