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Re: ARM patch: Keep track of condition codes in Thumb-1 mode
- From: Bernd Schmidt <bernds at codesourcery dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Cc: Richard Earnshaw <rearnsha at arm dot com>
- Date: Fri, 09 Jul 2010 13:46:17 +0200
- Subject: Re: ARM patch: Keep track of condition codes in Thumb-1 mode
- References: <4C32F72A.email@example.com>
On 07/06/2010 11:28 AM, Bernd Schmidt wrote:
> A few weeks ago I changed the cbranchsi4_insn pattern so that it can
> take advantage of a compare insn output by a previous conditional
> branch. This patch extends the mechanism to keep track of more kinds of
> cc-setting insns, in a way similar to that used on cc0 ports.
I wouldn't normally ping this after a few days, but...
> Discouraging the second alternative of
> the cbranchsi4_insn pattern tends to make reload work better:
> - mov r3, #0
> - mov r8, r0
> mov r5, r7
> - cmp r8, r3
> + mov r8, r0
> + cmp r0, #0
See my earlier post from today. I've now found the real problem in
reload and will drop this part of the patch.