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Re: ARM patch: Split compare_scc (PR42835)

On 03/07/10 12:46, Bernd Schmidt wrote:

Beside adding the peephole, this clears up some oddities elsewhere.
There were several adc patterns with noncanonical RTL (plus inside plus
not the first operand).  Now that we have a CC_NOTB code, I've added a
code_iterator to enable adc to use that as well.  Also, the subsi3
pattern didn't allow all the operand combinations supported by the
machine.  These are changes I also need for other work, so it would be
nice if they were approved quickly so I don't have to submit them with
multiple patches.

Last time I looked, the rules on canonicalization just said that "the more complex operation went first". In practice that meant that a constant was always last, and a register was always placed after an operation that took sub-operands.

It's thus not entirely clear that plus must come before ltu in a pattern, and these patterns were almost certainly created because they matched real RTL generated by the mid-end of the compiler. So have the mid-end rules been tightened? Actually, looking at commutative_operand_precedence the answer may well be yes (though there are clearly still some ambiguities -- should not come before neg, for example?).

That means there may well be several other patterns in the machine description that are no-longer matching properly. And others that might well be redundant. Sigh!

Will review patch itself momentarily.


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